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Principal Asic Jobs

14 open positions · Updated 2 weeks ago

Average salary: 205k–292.1k/yr

Showing 14 of 14 positions

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Principal ASIC Design Verification Engineer (Starshield) Visa

SpaceX Irvine, CA $200k–$285k/yr Published 1 month ago

Python UVM SystemVerilog MATLAB

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Principal ASIC Design Verification Engineer (Starshield) Visa

SpaceX Palo Alto, CA $210k–$295k/yr Published 1 month ago

Python UVM SystemVerilog MATLAB

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Principal ASIC Design Verification Engineer (Starshield) Visa

SpaceX Hawthorne, CA $200k–$285k/yr Published 1 month ago

Python UVM SystemVerilog MATLAB

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Principal ASIC Design Engineer (Starshield) Visa

SpaceX Irvine, CA $200k–$285k/yr Published 1 month ago

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

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Principal ASIC Design Engineer (Starshield)

SpaceX Palo Alto, CA $210k–$295k/yr Published 1 month ago

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

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Principal ASIC Design Engineer (Starshield) Visa

SpaceX Hawthorne, CA $200k–$285k/yr Published 1 month ago

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

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Principal DFT Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal DFT Engineer to lead the development of next-generation ASICs for the Starlink network.

SpaceX USA $200k–$285k/yr Published 19 hours ago

C++ Verilog Siemens Tessent RTL DFT

Flexible on stack

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Principal DFT Engineer (Silicon Engineering) Visa

Lead the implementation and optimization of DFT architectures for next-generation ASICs at SpaceX.

SpaceX USA Published 19 hours ago

C++ Verilog Siemens Tessent ATE RTL

Flexible on stack

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Principal DFT Engineer (Silicon Engineering) Visa

SpaceX Sunnyvale, CA $210k–$295k/yr Published 3 months ago

C++ Verilog Siemens Tessent UPF RTL

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Principal Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX USA Published 1 day ago

FPGA ASIC VMM Python UVM

Flexible on stack

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Principal Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX USA $210k–$310k/yr Published 1 day ago

FPGA ASIC VMM Python UVM

Flexible on stack

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Principal Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX USA $210k–$300k/yr Published 1 day ago

FPGA ASIC VMM Python UVM

Flexible on stack

Apply →

Principal Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX USA $210k–$300k/yr Published 1 day ago

FPGA ASIC VMM Python UVM

Flexible on stack

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Principal RFIC Engineer (Starshield Silicon) Visa

SpaceX Hawthorne, CA $200k–$285k/yr Published 3 months ago

Filters demodulators RF GaAs IC design

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