Principal Asic Jobs

54 open positions · Updated 2 weeks ago

Average salary: 179.6k–267.0k/yr

54 roles Senior 26, Mid 12, Principal 8, Lead 5, Junior 3 1–10 yrs experience Austin, TX +10 more Full-time newest 2 days ago

Also hiring: Python CMOS FPGA Perl Verilog RFIC

Showing 8 of 8 positions

Search with filters →

Principal Engineer, AI Satellites (Starmind) Visa

Join SpaceX as a Principal Engineer to develop cutting-edge RFICs for the Starmind satellite constellation.

SpaceX Bastrop, TX Published 2 weeks ago

RF Analog Mixed-Signal DSP microwave

Apply →

Principal DFT Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal DFT Engineer to develop next-generation ASICs for the Starlink network, enhancing global connectivity.

SpaceX Palo Alto, CA $220k–$355k/yr Published 3 weeks ago

C++ Verilog Siemens Tessent DFT ASIC

Flexible on stack

Apply →

Principal DFT Engineer (Silicon Engineering) Visa

Lead the implementation and optimization of DFT architectures for next-generation ASICs at SpaceX.

SpaceX Austin, TX Published 3 weeks ago

C++ Verilog Siemens Tessent UPF DFT

Flexible on stack

Apply →

Principal DFT Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal DFT Engineer to lead the development of next-generation ASICs for the Starlink network.

SpaceX Irvine, CA $210k–$340k/yr Published 3 weeks ago

C++ Verilog Siemens Tessent DFT ASIC

Flexible on stack

Apply →

Principal Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Palo Alto, CA $210k–$310k/yr Published 3 months ago

FPGA ASIC VMM Python UVM

Flexible on stack

Apply →

Principal Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Austin, TX Published 3 months ago

FPGA ASIC VMM Python UVM

Flexible on stack

Apply →

Principal Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Redmond, WA $210k–$300k/yr Published 3 months ago

FPGA ASIC VMM Python UVM

Flexible on stack

Apply →

Principal Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Irvine, CA $210k–$300k/yr Published 3 months ago

FPGA ASIC VMM Python UVM

Flexible on stack

Apply →