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Systemverilog Jobs in Palo Alto

1 open positions · Updated 1 week ago

Average salary: 135k–210k/yr

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Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Palo Alto, CA $135k–$210k/yr Published 2 weeks ago

Python UVM SystemVerilog MATLAB

Flexible on stack

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