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Uvm Jobs in Palo Alto

3 open positions · Updated 2 weeks ago

Average salary: 173.3k–266.7k/yr

Showing 3 of 3 positions

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SpaceX
Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Palo Alto, CA $135k–$210k/yr Published 2 weeks ago
Python UVM SystemVerilog MATLAB
Flexible on stack
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SpaceX
Sr. ASIC Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Palo Alto, CA $175k–$280k/yr Published 2 weeks ago
ASIC VMM Python UVM OVM
Flexible on stack
Apply →
SpaceX
Principal Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Palo Alto, CA $210k–$310k/yr Published 2 months ago
FPGA ASIC VMM Python UVM
Flexible on stack
Apply →

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