Chip Design Engineer
Join Ricursive Intelligence as a Chip Design Engineer to architect AI-driven physical design flows for advanced chip development.
Posted by employer 1 day ago
First seen on Joblaze 1 week ago
Last verified on the company career page 1 day ago
AI in the day-to-day
Deploy and extend AI tooling across the flow, including AI-driven design-space optimization and ML-based PPA improvement.
Requirements
- Experience
- 10+ years
- Education
- Bachelor's degree
Not disclosed in this posting: compensation, work arrangement, visa sponsorship.
Joblaze summary
In this role, the Chip Design Engineer at Ricursive Intelligence will focus on architecting and optimizing the physical design flow from RTL to GDSII, ensuring that complex blocks meet stringent performance and power requirements. The position demands extensive experience with EDA tools and scripting in Python and Tcl, as well as a proven track record in chip design and tapeout at advanced nodes. Ideal candidates will have over a decade of hands-on experience in physical design, particularly in high-performance computing environments, and a strong background in AI-driven methodologies. As part of a small, early-stage team, this engineer will play a crucial role in defining the design process
Joblaze insights
- Listed 7 days ago on Joblaze — tracked directly from Ricursive Intelligence's career page.
- Ricursive Intelligence has 12 other open roles including Software Engineer, Chip Design, RTL and Design Verification Engineer, Ricursive at DAC 2026 — Introduce Yourself.
- 6527 active Python roles on Joblaze right now.
- 5148 active AI/ML roles on Joblaze right now.
- 55 active TCL roles on Joblaze right now.
- Typical Python salary we track runs $125,000–$190,800 (median $160,000, across 3229 roles). See Python salary trends
Quick facts
- How much experience is required?
- At least 10 years of relevant experience for this Chip Design Engineer role.
- What's the tech stack?
- Joblaze extracted these technologies from the posting: AI/ML, EDA, Python, TCL, VLSI.
- What seniority level is this role?
- Ricursive Intelligence targets senior candidates for this position.
- Is this full-time or contract?
- Full-time for this Chip Design Engineer role at Ricursive Intelligence.
From the original posting
Ricursive Intelligence is a frontier AI lab building self-improving systems, starting with chip design. We are reinventing chip development and closing the loop between AI and the hardware that fuels it, recursively accelerating the path to artificial superintelligence. Backed by $335M from Sequoia, Lightspeed, DST, and NVIDIA Ventures, we are a small and fast-paced team where every hire shapes the work.
The company has unmatched talent density, including IMO, IPHO, and IOAA gold medalists, pioneers who made prior breakthroughs in chip design: AlphaChip (Nature 2021), ePlace (DAC Best Paper Nominee 2014), RL-CCD (DAC Best Paper 2023), INSTA (DAC Best Paper 2025), and C3PO (ASP-DAC Best Paper 2026), chip leads for Apple (iPhone, iPad, M1) and Google (TPU, OpenTitan), and top researchers and engineers from Anthropic, Google DeepMind, Stanford, and MIT.
ABOUT THE ROLE
We are hiring an engineer who deeply understands every step of the flow, from synthesis through tapeout, and who has personally fought complex blocks to closure at an advanced node. Your expertise will guide the design of self-improving systems that you will then use to build real silicon.
WHAT YOU WILL DO
Contribute to synthesis, DFT insertion, floorplanning, PDN design, placement, CTS, routing, and all electrical, timing, and physical signoff.
Own timing, power, and physical closure of the most complex, PPA-critical blocks in advanced nodes, driving multi-mode multi-corner timing convergence, EM/IR signoff, and DRC/LVS closure through final ECOs and tapeout.
Partner cross-functionally on chip design infrastructure and automation, optimization techniques and goals, and design improvement strategies.
MINIMUM QUALIFICATIONS
BS in Electrical Engineering, Computer Engineering, Computer Science, or a closely related technical field.
5+ years of hands-on physical design experience spanning every step of the flow (synthesis, floorplanning, PDN, placement, CTS, routing, STA, extraction, power/EM/IR analysis, physical verification, LEC, and ECO), including experience architecting hierarchical flows both top-down and bottom-up.
Day-one fluency in at least one production implementation and signoff stack with chip design tools and strong Tcl and Python scripting.
Track record of successful chip design and tapeout: owned closure of complex blocks, subsystems, or full chips through complete signoff in advanced technology nodes, on silicon that taped out and shipped to production.
PREFERRED QUALIFICATIONS
Masters or PhD in EE, CE, CS, or a related field, with a focus on VLSI, physical design, or EDA/CAD algorithms.
Deep expertise in high-performance compute silicon (e.g., ML accelerators, CPUs, GPUs, or large SoCs), including multi-voltage domain (UPF) design and 2.5D/3D integration with bump/RDL planning.
Publications at major conferences (e.g., DAC, ICCAD, ISPD, DATE) demonstrating research strength in physical design or AI for chip design.