DFT Engineer

ABOUT THE ROLE

A self-improving chip design system is only as good as the silicon it produces, and silicon only counts once it has been tested, screened, and shipped. We are hiring a DFT engineer who treats testability as a first-class design discipline: someone who has architected the scan, MBIST, and boundary-scan infrastructure for complex chips at advanced nodes, generated and signed off the patterns that qualified them, and then stood at the tester when first silicon came back. Your expertise will teach our systems how to reason about test coverage, test cost, and yield, and you will use those systems to build real silicon.

You will own DFT end to end at Ricursive: DFT architecture and insertion, MBIST planning, fault-model analysis, and ATPG signoff in pre-silicon, then hands-on CP, FT, and SLT bring-up with our foundry and OSAT partners in post-silicon. You will work shoulder to shoulder with the RTL, DV, and physical design engineers, flex into RTL and DV work when the program needs it, and bring AI tools into the traditional DFT flow wherever they make the work faster or the silicon better. As part of a small team, you will have the opportunity to define our foundational DFT methodology and infrastructure from the ground up.

WHAT YOU WILL DO

• Own DFT architecture and insertion for complex silicon at advanced nodes: hierarchical scan and compression, BIST, MBIST and BISR planning and repair, boundary scan, and IJTAG networks (IEEE 1149.1, etc), integrated with the synthesis, physical design, and STA flow from RTL to GDS.

• Define the fault-model and coverage strategy (stuck-at, transition, path-delay, cell-aware, and bridging) and own ATPG generation, fault simulation, coverage closure, pattern verification in zero-delay and SDF gate-level simulation, and DFT signoff to tapeout, making explicit tradeoffs between coverage, test time, pattern count, and area.

• Drive post-silicon test from first silicon to production: ATE pattern conversion and bring-up, CP (wafer sort), FT, and SLT program development and debug, scan diagnosis and failure analysis, and yield and DPPM improvement, working hands-on with our foundry and OSAT partners.

• Integrate DFT with RTL, DV, and physical design: set DFT requirements at the micro-architecture stage, verify test logic alongside functional verification, close test-mode timing with the PD and STA engineers, and take on RTL design and DV work directly when the program needs it.

• Make DFT AI-native: shape how AI plans, closes and debugs DFT, measured in coverage, test time and DPPM.

• Partner cross-functionally on chip design infrastructure and automation, encoding DFT knowledge as reusable flows, checks, and evaluation targets that the rest of the team and our AI systems can build on.

MINIMUM QUALIFICATIONS

• BS in Electrical Engineering, Computer Engineering, Computer Science, or a closely related technical field.

• 5+ years of hands-on DFT experience owning the full lifecycle on complex SoCs or IPs: DFT architecture and specification, scan and compression insertion, MBIST and BISR, boundary scan and IJTAG, test-mode timing constraints, DFT verification and DRC closure, fault-model and coverage analysis, and ATPG pattern generation and signoff.

• Day-one fluency in at least one production DFT stack and gate-level simulation, with strong Tcl and Python scripting and enough Verilog/SystemVerilog to write and debug test logic and testbenches yourself.

• Post-silicon experience on silicon that taped out and shipped to production: converted and brought up ATPG and MBIST patterns on ATE, debugged CP, FT, and SLT failures, and worked directly with foundry and OSAT partners.

• Practical, demonstrated use of AI coding and agentic tools in your own engineering work, with clear ideas about where they help in a DFT flow and where they do not.

PREFERRED QUALIFICATIONS

• Masters or PhD in EE, CE, CS, or a related field, with a focus on VLSI test, fault tolerance and reliability, or EDA/CAD algorithms.

• Deep expertise in high-performance compute silicon (e.g., ML accelerators, CPUs, GPUs, or large SoCs), including DFT for advanced packaging.

• Product and test engineering depth: test program development, characterization and screens (HVS, HTOL), yield analytics and wafer-map correlation, outlier screening, and RMA and failure analysis.

• Demonstrated and quantified gains from AI/ML in a chip design or test flow, experience building or extending AI-assisted design and verification flows.

• Publications at major conferences (e.g., ITC, VTS, DAC, ICCAD, DATE) or open-source contributions in DFT, test, or AI for chip design.