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Eda Jobs

30 open positions · Updated 1 week ago

Average salary: 172.4k–239.6k/yr

Showing 20 of 30 positions

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Sr. ASIC Design Engineer (Starshield)

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

Hawthorne, CA

$160k–$225k/yr

Published 3 weeks ago Apply →

Sr. ASIC Design Engineer (Starshield)

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

Palo Alto, CA

$170k–$235k/yr

Published 2 weeks ago Apply →

Product Manager, New Grad (2026) - Amsterdam Remote

Amsterdam, Netherlands

Published 7 months ago Apply →

Data Scientist Remote

AWS Snowflake Tableau Redshift Airflow

Denver, Colorado, United States

$136k–$184k/yr

Published 3 months ago Apply →

Sr. ASIC Design Engineer (Silicon Engineering) Visa

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

Sunnyvale, CA

$170k–$235k/yr

Published 4 months ago Apply →

Sr. ASIC Design Engineer (Silicon Engineering) Visa

Quartus II Xilinx Vivado Verilog AHB IES

Redmond, WA

$160k–$225k/yr

Published 4 months ago Apply →

Principal ASIC Design Engineer (Starshield) Visa

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

Hawthorne, CA

$200k–$285k/yr

Published 3 weeks ago Apply →

Principal ASIC Design Engineer (Starshield)

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

Palo Alto, CA

$210k–$295k/yr

Published 2 weeks ago Apply →

Principal ASIC Design Engineer (Silicon Engineering) Visa

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

Sunnyvale, CA

$210k–$295k/yr

Published 4 months ago Apply →

Principal ASIC Design Engineer (Silicon Engineering) Visa

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

Redmond, WA

$200k–$285k/yr

Published 3 months ago Apply →

Principal ASIC Design Engineer (Silicon Engineering) Visa

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

Irvine, CA

$200k–$285k/yr

Published 4 months ago Apply →

Sr. ASIC Design Engineer (Silicon Engineering) Visa

Verilog AHB ASIC Python System Verilog

Irvine, CA

$160k–$225k/yr

Published 1 month ago Apply →

Product Manager, New Grad (2026) - Berlin

Berlin, Germany

Published 7 months ago Apply →

Physical Design Engineer II (Silicon Engineering) Visa

FinFET EDA RTL Makefile ASIC

Bastrop, TX

Published 1 week ago Apply →

Physical Design Engineer II (Silicon Engineering) Visa

FinFET RTL Makefile ASIC Python

Irvine, CA

$145k–$175k/yr

Published 1 week ago Apply →

Physical Design Engineer (Silicon Engineering) Visa

FinFET Makefile bash ASIC Python

Sunnyvale, CA

$135k–$185k/yr

Published 4 months ago Apply →

Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) Visa

Scan LBIST FinFET EDA Makefile

USA

Published 3 months ago Apply →

IC Package Engineer (Starlink/Akoustis) Visa

QFN WLP ANSYS CSP EDA

Bastrop, TX

Published 3 months ago Apply →

Sr. Full Chip Physical Design Engineer (Silicon Engineering) Visa

Verilog FinFET EDA Makefile DFT

Sunnyvale, CA

$170k–$235k/yr

Published 3 months ago Apply →

Sr. ASIC Validation Engineer (Silicon Engineering) Visa

PCIe C++ JTAG FPGA ASIC

Redmond, WA

$160k–$225k/yr

Published 3 months ago Apply →

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