Is the DFT Intern role remote?

No — this is an on-site role in San Jose.

Where is the role based?

Etched is hiring for this position in San Jose.

What's the tech stack?

Joblaze extracted these technologies from the posting: Python, SystemVerilog, TCL, Verilog.

What seniority level is this role?

Etched targets intern candidates for this position.

Is this full-time or contract?

Internship for this DFT Intern role at Etched.

DFT Intern at Etched

Joblaze summary

In the DFT Intern role at Etched, the intern will assist in enhancing DFT flow automation and support chip-level regression efforts, collaborating with both frontend and backend design teams. Key skills include familiarity with hardware description languages like Verilog or SystemVerilog, as well as exposure to ASIC or SoC design concepts and scripting languages such as Python or Tcl. This position is suitable for students pursuing degrees in electrical or computer engineering, particularly those eager to learn in a fast-paced environment. Etched emphasizes a collaborative culture where engineering and research intersect, providing direct mentorship from experienced professionals.

Joblaze insights

Listed 4 days ago — first seen on Joblaze September 21, 2026. Last confirmed on Etched's careers page September 25, 2026.
Python appears in 16.6% of 572 comparable intern other roles in United States; TCL appears in 0.7% of 572 comparable intern other roles in United States.

Quick facts

Is the DFT Intern role remote?: No — this is an on-site role in San Jose.
Where is the role based?: Etched is hiring for this position in San Jose.
What's the tech stack?: Joblaze extracted these technologies from the posting: Python, SystemVerilog, TCL, Verilog.
What seniority level is this role?: Etched targets intern candidates for this position.
Is this full-time or contract?: Internship for this DFT Intern role at Etched.

From the original posting

Job Summary

As a DFT Intern at Etched, you will help review and refine DFT flow automation to support chip-level regression on Caelius. You will work across frontend and backend design teams, contribute to DFT verification (including MBIST, Scan, BSCAN, and SSN simulations), and develop flows for various ATPG fault models. You do not necessarily need prior DFT experience; just the ability to learn quickly in a fast-paced, high-autonomy environment. We are looking for Summer '26, Fall '26, Spring '27, and Summer '27 interns.

You may be a good fit if you have

Progress towards a Bachelor's, Master's, or PhD degree in electrical engineering, computer engineering, or a related field.
Familiarity with a hardware description language (Verilog or SystemVerilog)
Exposure to ASIC or SoC design concepts
Familiarity with digital logic design fundamentals
Familiarity with standard ASIC design flow steps (synthesis, STA, DFT)
Familiarity with scripting in Python, Tcl, or another language
Are able to learn quickly about transformers and other aspects of modern artificial intelligence

Strong candidates may also have experience with

Knowledge of DFT concepts such as MBIST, scan insertion, and scan compression
Experience with Tessent or similar DFT tooling
Familiarity with ATPG fault models (SAF, TDF, BDF, IDDQ, PDF)
Exposure to DFT flow automation or regression infrastructure
Familiarity with clocking and reset schemes

We encourage you to apply even if you do not believe you meet every single qualification.

Program details

12-week paid internship
Generous housing support for those relocating
Daily lunch and dinner in our office
Based at our office in San Jose, CA
Direct mentorship from industry leaders and world-class engineers
Opportunity to work on one of the most important problems of our time

For any questions, contact internships@etched.com.

Standard company text repeated across Etched's postings is omitted here.

DFT Intern

Similar positions