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FPGA Engineer

Join Astranis as an FPGA Engineer to design and verify high-performance systems for advanced satellites.

Location
San Francisco
Compensation
$140k–$205k/yr
Level
mid
Type
full time · On-site

Posted by employer 2 years ago

First seen on Joblaze 1 month ago

Last verified on the company career page 1 day ago

Apply at Astranis → Save job Scanned from astranis.com

Requirements

Experience
2+ years
Education
Bachelor's degree
Visa
Sponsorship available

Benefits

401k Match Unlimited PTO Equity/Stock Options On-site Meals Health Insurance

Joblaze summary

The FPGA Engineer at Astranis plays a crucial role in designing and verifying RTL for high-performance systems used in spacecraft, collaborating closely with software and hardware teams to meet stringent design requirements. Proficiency in Verilog, experience with FPGAs, and a background in hardware development are essential for success in this position. This role is well-suited for engineers with at least two years of experience who thrive in fast-paced environments and have a passion for innovative technology. Astranis is rapidly expanding, offering a dynamic workplace focused on advanced satellite communications.

Joblaze insights

  • Listed about a month ago — first seen on Joblaze September 3, 2026. Last confirmed on Astranis's careers page October 27, 2026.
  • Salary band is in line with the typical range for comparable tech roles (median ~$130,000).
  • Starts above 96% of 25 comparable mid other roles in United States that list RF we track (median $125,000 across 5 companies).
  • RF appears in 1.4% of 3194 comparable mid other roles in United States; TCL appears in 0.3% of 3194 comparable mid other roles in United States.

Quick facts

Is the FPGA Engineer role remote?
No — this is an on-site role in San Francisco.
What's the salary range?
Astranis lists $140,000–$205,000 for this role.
How much experience is required?
At least 2 years of relevant experience for this FPGA Engineer role.
Where is the role based?
Astranis is hiring for this position in San Francisco.
What's the tech stack?
Joblaze extracted these technologies from the posting: ADC, DAC, DSP, JESD204, RF, SystemVerilog.
Does Astranis sponsor work visas for this role?
Yes — the posting indicates visa sponsorship is available for the right candidate.
What seniority level is this role?
Astranis targets mid-level candidates for this position.
Is this full-time or contract?
Full-time for this FPGA Engineer role at Astranis.

From the original posting

Astranis builds advanced satellites for high orbits, expanding humanity’s reach into the solar system. Today Astranis satellites provide dedicated, secure networks to highly-sophisticated customers across the globe – large enterprises, sovereign governments, and the US military.

FPGA Engineer

As an FPGA Engineer you'll be responsible for the architecture, the design, the verification, and test of RTL designs for the FPGAs that go into the spacecraft. You will work closely with the software, DSP and hardware teams to achieve design requirements.

Role

  • Design RTL for high performance systems including software defined radios, avionics and ground systems, for commercial and US Government projects
  • Work with multiple FPGAs and toolchains
  • Interface FPGAs with high speed data converters, memories, MCUs
  • Design, implement and test radiation mitigation schemes on FPGA
  • Collaborate closely with DSP/radio algorithm designer
  • Collaborate closely with embedded firmware and software engineers
  • Assist in recruiting, interviewing, and hiring additional teammates to our rapidly-growing team.

Requirements

  • US Citizenship or Green Card (This is a legal requirement; no exceptions)
  • Bachelor of Science degree in electrical engineering, computer science, computer engineering, or equivalent
  • 2+ years of experience
  • A passion for hardware development, including working in a fast-paced environment and hands-on design and development
  • Experience in designing, implementing, verifying and testing high throughput systems implemented on FPGAs
  • Strong proficiency with Verilog (preferably SystemVerilog) for both synthesis and verification

Bonus

  • MS or PhD in computer engineering or equivalent
  • Experience in at least 1 domain beyond just the logic design. This could be DSP/radio design, software, hi-reliability design (e.g. fault analysis & recover), etc.
  • Experience with Xilinx FPGAs
  • Experience with modern communication systems (RF, IF/IQ, time/freq domains, modulation)
  • Experience with Vivado IDE, TCL
  • Familiarity with system level estimates and implications of power, thermal, and real estate
  • Experience with high speed data converters (ADCs, DACs, JESD204)
  • Experience with circuit level debugging
  • Experience with digital communication theory and implementation, such as LDPC implementations
  • Experience with space-based systems
  • Experience with UVM

What we offer:
All our positions offer a compensation package that includes equity and robust benefits.

Base pay is just one component of Astranis’s total rewards package. Your compensation also includes a significant equity package via incentive stock options, high-quality company-subsidized healthcare, disability and life insurance, 401(k) retirement planning, flexible PTO, and free on-site catered meals.

Astranis pay ranges are informed and defined through professional-grade salary surveys and compensation data sources. The actual base salary offered to a successful candidate will additionally be influenced by a variety of factors including experience, credentials & certifications, educational attainment, skill level requirements, and the level and scope of the position.
Base Salary
$140,000—$205,000 USD
U.S. Citizenship, Lawful Permanent Residency, or Refugee/Asylee Status Required

Astranis SMS Terms of Service

  1. Recruiting Updates: By opting in, you agree to receive SMS updates, interview coordination, and recruiting communications from Astranis Space Technologies Corp.

Standard company text repeated across Astranis's postings is omitted here.

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