Is the PD Intern role remote?

No — this is an on-site role in San Jose, California, United States.

Where is the role based?

Etched is hiring for this position in San Jose, California, United States.

What's the tech stack?

Joblaze extracted these technologies from the posting: ASIC, Python, SoC, SystemVerilog, UVM.

What seniority level is this role?

Etched targets intern candidates for this position.

Is this full-time or contract?

Internship for this PD Intern role at Etched.

PD Intern at Etched

Joblaze summary

In the role of Physical Design intern at Etched, the individual will focus on translating front-end designs into silicon, enhancing the speed of the design process towards final signoff. Key skills include familiarity with high-speed digital logic, ASIC or SoC design concepts, and proficiency in SystemVerilog, UVM, or Python. This position is ideal for students pursuing degrees in electrical or computer engineering, particularly those with a strong foundation in physical design flows and verification. Etched emphasizes a collaborative environment where engineering and research intersect, providing interns with direct mentorship from experienced professionals.

Joblaze insights

Listed yesterday — first seen on Joblaze September 21, 2026. Last confirmed on Etched's careers page September 21, 2026.
Python appears in 35.7% of 56 comparable intern ai/ml roles in United States; SoC appears in 3.6% of 56 comparable intern ai/ml roles in United States.

Quick facts

Is the PD Intern role remote?: No — this is an on-site role in San Jose, California, United States.
Where is the role based?: Etched is hiring for this position in San Jose, California, United States.
What's the tech stack?: Joblaze extracted these technologies from the posting: ASIC, Python, SoC, SystemVerilog, UVM.
What seniority level is this role?: Etched targets intern candidates for this position.
Is this full-time or contract?: Internship for this PD Intern role at Etched.

From the original posting

Job Summary

As a Physical Design intern for Etched, you will be responsible for realizing our front-end designs in silicon, helping Etched to improve iteration speed to final signoff. You will assist in developing and running Physical Design flows to synthesize blocks, automate final design checks, and advise RTL design decisions. We are looking for Fall '26, Spring '27, and Summer '27 interns.

You may be a good fit if you have

Progress towards a Bachelor’s, Master’s, or PhD degree in electrical engineering, computer engineering, or a related field.
Familiarity with high-speed digital logic
Exposure to ASIC or SoC design concepts
Familiarity with SystemVerilog, UVM, or Python
Familiarity with verification work and writing test benches
Familiarity with physical design flows and tooling
Are able to learn quickly about transformers and other aspects of modern artificial intelligence

Strong candidates may also have experience with

Familiarity with modern ML and LLM model architectures
Familiarity with numerical representations and functions (RTL)
Familiarity with clocking and reset schemes (RTL/PD)
UVM or formal verification experience (DV)
Ability to program with Python or another scripting language

We encourage you to apply even if you do not believe you meet every single qualification.

Program details

12-week paid internship
Generous housing support for those relocating
Daily lunch and dinner in our office
Based at our office in San Jose, CA
Direct mentorship from industry leaders and world-class engineers
Opportunity to work on one of the most important problems of our time

For any questions, contact internships@etched.com

Standard company text repeated across Etched's postings is omitted here.

PD Intern

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