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Verilog Jobs in Palo Alto

4 open positions · Updated 16 hours ago

Average salary (USD/year): 166.3k–246.3k/yr
4 roles Mid 2, Principal 1, Senior 1 1–10 yrs experience Palo Alto, CA, Palo Alto, CA, United States Full-time newest 16 hours ago
Also hiring: ASIC Python C++ DFT System Verilog SystemVerilog

Showing 4 of 4 positions

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SpaceX
Sr. ASIC Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Palo Alto, CA, United States $175k–$280k/yr Published 1 day ago
Verilog ASIC Python System Verilog SoC
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SpaceX
ASIC Design Engineer (Silicon Engineering) Visa

Join SpaceX as an ASIC Design Engineer to develop cutting-edge FPGAs and ASICs for the Starlink broadband internet system.

SpaceX Palo Alto, CA, United States $135k–$175k/yr Published 1 day ago
C++ Xilinx Vivado Verilog DSP HDL simulators
Flexible on stack
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SpaceX
ASIC/SOC DFT Engineer (Silicon Engineering) Visa

Join SpaceX as an ASIC/SOC DFT Engineer to develop cutting-edge ASICs for the Starlink network, enabling global connectivity.

SpaceX Palo Alto, CA $135k–$175k/yr Published 2 months ago
Verilog UPF RTL DFT ASIC
Flexible on stack
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SpaceX
Principal DFT Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal DFT Engineer to develop next-generation ASICs for the Starlink network, enhancing global connectivity.

SpaceX Palo Alto, CA $220k–$355k/yr Published 2 months ago
C++ Verilog Siemens Tessent DFT ASIC
Flexible on stack
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