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Verilog Jobs in Palo Alto

4 open positions · Updated 1 week ago

Average salary: 165k–235k/yr
4 roles Junior 1, Mid 1, Principal 1, Senior 1 1–10 yrs experience Palo Alto, CA Full-time newest 1 week ago
Also hiring: ASIC Python SystemVerilog DFT RTL ADS

Showing 4 of 4 positions

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SpaceX
New Graduate Engineer, Silicon Engineering Visa

Join SpaceX as a New Graduate Engineer in Silicon Engineering, working on next-gen silicon for the Starlink program.

SpaceX Palo Alto, CA $135k–$175k/yr Published 1 week ago
ADS Verilog HFSS RTL Momentum
Flexible on stack
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SpaceX
ASIC/SOC DFT Engineer (Silicon Engineering) Visa

Join SpaceX as an ASIC/SOC DFT Engineer to develop cutting-edge ASICs for the Starlink network, enabling global connectivity.

SpaceX Palo Alto, CA $135k–$175k/yr Published 2 weeks ago
Verilog UPF RTL DFT ASIC
Flexible on stack
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SpaceX
Principal DFT Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal DFT Engineer to develop next-generation ASICs for the Starlink network, enhancing global connectivity.

SpaceX Palo Alto, CA $220k–$355k/yr Published 3 weeks ago
C++ Verilog Siemens Tessent DFT ASIC
Flexible on stack
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SpaceX
Sr. RTL Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. RTL Design Engineer to develop cutting-edge ASICs for the Starlink network, enabling global connectivity.

SpaceX Palo Alto, CA $170k–$235k/yr Published 3 months ago
Verilog ASIC Python System Verilog SoC
Flexible on stack
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