Join Anthropic as a Research Engineer to advance AI models' silicon design capabilities within a collaborative team.
Posted by employer 1 day ago
First seen on Joblaze 1 hour ago
Last verified on the company career page 1 hour ago
What you'll build
- Invent RL environments for RTL generation
- Implement design verification processes
- Optimize physical design
- Conduct experiments
- Collaborate with researchers and engineers
Must have
- Expertise in ASIC or FPGA design
- Fluent with industry EDA tools
- Experience with RTL and design verification
- Taped out chips
Nice to have
- Experience with reinforcement learning
- Built tooling around chip design flows
- Worked on ML accelerators
- Familiarity with high-level synthesis
Practical constraints
- In-office at least 25% of the time
Requirements
- Education
- Bachelor's degree
- Visa
- Sponsorship available
Not disclosed in this posting: years of experience.
Benefits
Joblaze summary
In the role of Research Engineer for the Code RL team at Anthropic, the individual will focus on enhancing AI models' capabilities in chip design through the development of reinforcement learning environments and evaluations. Key skills include expertise in ASIC or FPGA design, familiarity with EDA tools, and a strong background in both research and engineering implementation. This position is well-suited for candidates with significant experience in hardware design and a passion for advancing AI technologies. Anthropic emphasizes collaboration across teams to ensure the safe and effective deployment of their AI systems.
Joblaze insights
- Listed today — first seen on Joblaze October 23, 2026. Last confirmed on Anthropic's careers page October 23, 2026.
- Salary band is above the typical range for AI/ML roles (median ~$190,000).
- Starts above 97% of 184 comparable mid ai/ml roles in United States we track (median $150,000 across 69 companies).
- reinforcement learning appears in 4.1% of 466 comparable mid ai/ml roles in United States; UVM appears in 0.2% of 466 comparable mid ai/ml roles in United States.
Quick facts
- Is the Research Engineer, Chip Design RL role remote?
- It's hybrid — Anthropic expects some on-site time in San Francisco, CA, United States.
- What's the salary range?
- Anthropic lists $500,000–$850,000 for this role.
- Where is the role based?
- Anthropic is hiring for this position in San Francisco, CA, United States.
- What's the tech stack?
- Joblaze extracted these technologies from the posting: ASIC, EDA, FPGA, RTL, UVM, reinforcement learning.
- Does Anthropic sponsor work visas for this role?
- Yes — the posting indicates visa sponsorship is available for the right candidate.
- What seniority level is this role?
- Anthropic targets mid-level candidates for this position.
- Is this full-time or contract?
- Full-time for this Research Engineer, Chip Design RL role at Anthropic.
From the original posting
About Anthropic
About the RL teams
Our Reinforcement Learning teams lead Anthropic's reinforcement learning research and development, playing a critical role in advancing our AI systems. We've contributed to all Claude models, with significant impacts on the autonomy and coding capabilities of Claude Fable 5.1 and Claude Opus 5.5. Our work spans several key areas:
- Developing systems that enable models to use computers effectively
- Advancing code generation through reinforcement learning
- Pioneering fundamental RL research for large language models
- Building scalable RL infrastructure and training methodologies
- Enhancing model reasoning capabilities
We collaborate closely with Anthropic's alignment and frontier red teams to ensure our systems are both capable and safe. We partner with the applied production training team to bring research innovations into deployed models, and are dedicated to implementing our research at scale. Our Reinforcement Learning teams sit at the intersection of cutting-edge research and engineering excellence, with a deep commitment to building high-quality, scalable systems that push the boundaries of what AI can accomplish.
About the role
We're hiring for the Code RL team within the RL organization. As a Research Engineer, you'll advance our models' ability to design silicon. Hardware design is difficult and unforgiving – exactly the sort of domain we want Claude to excel at.
You'll leverage your chip design expertise and turn it into tasks and signals for models to learn from. Specifically, you will:
- Invent, design, and implement RL environments and evaluations for agentic RTL generation, design (including formal) verification, physical design optimization.
- Work on cross-cutting RL considerations such as EDA-tool latency optimization and proxy rewards.
- Conduct experiments and shape our roadmap.
- Deliver your work into research and production training runs.
- Collaborate with other researchers and engineers across and outside Anthropic.
You may be a good fit if you:
- Have expertise in ASIC or FPGA design: RTL, design verification (UVM, formal methods, coverage-driven), physical design (synthesis, place-and-route, timing closure), PPA optimization, DFT, ECOs.
- Are fluent with industry EDA tools and processes.
- Have taped out chips and have experience going from spec to silicon.
- Know how to balance research exploration with engineering implementation.
- Are passionate about AI's potential and committed to developing safe and beneficial systems.
Strong candidates may also have:
- Experience with reinforcement learning, evaluations or environments.
- Built tooling or automation around chip design flows.
- Worked on ML accelerators or high-performance compute hardware.
- Familiarity with high-level synthesis or architecture simulators.
The annual compensation range for this role is listed below.
Logistics
Standard company text repeated across Anthropic's postings is omitted here.