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Showing 7 of 7 results

SpaceX
Sr. RTL Design Engineer (Silicon Engineering) Visa
SpaceX Austin, TX Published 3 months ago
Verilog AHB ASIC Python System Verilog
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SpaceX
Principal DFT Engineer (Silicon Engineering) Visa

Lead the implementation and optimization of DFT architectures for next-generation ASICs at SpaceX.

SpaceX Austin, TX Published 3 weeks ago
C++ Verilog Siemens Tessent ATE RTL
Flexible on stack
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SpaceX
Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Austin, TX Published 3 weeks ago
Python UVM SystemVerilog MATLAB
Flexible on stack
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SpaceX
Sr. ASIC Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Austin, TX Published 3 weeks ago
ASIC VMM Python UVM OVM
Flexible on stack
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SpaceX
Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. SOC/ASIC Physical Design Engineer to develop cutting-edge silicon for space and ground infrastructures.

SpaceX Austin, TX Published 2 weeks ago
FinFET Scripting ASIC EDA tools physical design
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SpaceX
Physical Design Engineer II (Silicon Engineering) Visa
SpaceX Austin, TX Published 1 month ago
FinFET EDA RTL Makefile ASIC
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SpaceX
Principal Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Austin, TX Published 3 weeks ago
FPGA ASIC VMM Python UVM
Flexible on stack
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