UVM Jobs in Austin

8 open positions · Updated 1 month ago

8 roles Staff 3, Mid 2, Senior 2, Principal 1 1–12 yrs experience Austin +3 more Full-time newest 1 month ago

Also hiring: Python SystemVerilog ARM Perl RISC-V Verilog

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Design Verification Engineer - Internal IP Hybrid

Join Etched as a Design Verification Engineer to ensure high-performance custom IPs for cutting-edge AI hardware.

Etched Austin Published 6 months ago

Python UVM Perl TCL SystemVerilog

Flexible on stack

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Design Verification Engineer - Interface IP Hybrid

Join Etched as a Design Verification Engineer to tackle complex verification challenges in a fast-paced startup environment.

Etched Austin Published 6 months ago

PCIe ARC ARM UVM SystemVerilog

Flexible on stack

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Sr. Staff Engineer - Digital Design Verification Visa

Join Ambiq as a Sr. Staff Engineer to lead digital design verification for cutting-edge low-power semiconductor solutions.

Ambiq Austin, Texas, United States Published 5 months ago

APB Verilog ARM AHB C/C++

Flexible on stack

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Sr. Staff Engineer - Digital Design Verification Visa

Join Ambiq as a Sr. Staff Engineer to lead digital design verification for cutting-edge low-power semiconductor solutions.

Ambiq Austin, Texas, United States Published 2 months ago

APB Verilog ARM AHB C/C++

Flexible on stack

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Staff Engineer - Design Verification

Join Ambiq as a Staff Engineer to verify digital and mixed-signal designs for low-power semiconductor solutions.

Ambiq Singapore Published 4 months ago

C++ Verilog ARM C Makefile

Flexible on stack

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Sr. ASIC Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Austin, TX Published 3 months ago

ASIC VMM Python UVM OVM

Flexible on stack

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Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Austin, TX Published 3 months ago

Python UVM SystemVerilog MATLAB

Flexible on stack

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Principal Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Austin, TX Published 5 months ago

FPGA ASIC VMM Python UVM

Flexible on stack

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