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SpaceX
Sr. RTL Design Engineer (Silicon Engineering) Visa
SpaceX Austin, TX Published 2 months ago
Verilog AHB ASIC Python System Verilog
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SpaceX
Principal DFT Engineer (Silicon Engineering) Visa

Lead the implementation and optimization of DFT architectures for next-generation ASICs at SpaceX.

SpaceX Austin, TX Published 1 week ago
C++ Verilog Siemens Tessent ATE RTL
Flexible on stack
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