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Senior Verilog Jobs

13 open positions · Updated 5 days ago

Average salary (USD/year): 157.8k–246.5k/yr

13 roles Senior 13 5–8 yrs experience Austin, TX +12 more Full-time newest 5 days ago

Also hiring: Python SystemVerilog System Verilog FPGA ASIC C

13 Verilog roles across 8 companies, most in Other

Who is hiring (8 companies)

SpaceX (5) K2 Space (2) Ambiq (1) Astranis (1) Coreweave (1)

Role types

Other (12) AI/ML (1)

Work arrangement: 1 on-site · 12 not stated

Counts are open roles Joblaze currently tracks on company career pages for this exact skill/location; salaries are advertised minimums, annual, converted to USD.

Showing 13 of 13 positions

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Sr. FPGA Design Engineer

Join Reliable Robotics as a Sr. FPGA Design Engineer to enhance aviation safety through innovative technology.

Reliable Robotics Corporation Mountain View, CA Published 5 days ago

Verilog SystemVerilog VHDL

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DFT Engineer

Join Ricursive Intelligence as a DFT Engineer to shape the future of chip design with AI-driven methodologies.

Ricursive Intelligence Palo Alto Published 2 weeks ago

IJTAG Verilog DFT Python TCL

Flexible on stack

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Sr. ASIC Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Palo Alto, CA $175k–$280k/yr Published 2 weeks ago

Verilog ASIC Python System Verilog SoC

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Sr. ASIC Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Engineer to develop next-generation ASICs for space and ground infrastructures.

SpaceX Austin, TX Published 3 weeks ago

Verilog ASIC Python System Verilog SoC

Flexible on stack

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Sr. ASIC Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Engineer to develop cutting-edge ASICs for space and ground infrastructures.

SpaceX Irvine, CA $165k–$265k/yr Published 3 weeks ago

Verilog ASIC Python System Verilog SoC

Flexible on stack

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Sr. ASIC Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Engineer to develop next-generation ASICs for the Starlink network.

SpaceX Redmond, WA $165k–$270k/yr Published 3 weeks ago

Verilog ASIC Python System Verilog SoC

Flexible on stack

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ASIC Architect

Join Etched as an ASIC Architect to design next-generation AI accelerators with a focus on performance and efficiency.

Etched San Jose Published 1 year ago

C++ Verilog C gem5 AI/ML

Flexible on stack Heavy meetings

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Senior FPGA Engineer Visa

Join Astranis as a Senior FPGA Engineer to design and verify RTL for advanced satellite systems.

Astranis San Francisco $175k–$240k/yr Published 2 years ago

C++ Verilog C DSP Vivado

Flexible on stack

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Senior FPGA Prototyping Engineer

Join K2 Space as a Senior FPGA Prototyping Engineer to drive the development of next-gen communications ASICs in a fast-paced environment.

K2 Space United States - Remote $120k–$225k/yr Published 2 months ago

Verilog AMD UART JTAG Xilinx

Flexible on stack

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Senior FPGA Prototyping Engineer

Join K2 Space as a Senior FPGA Prototyping Engineer to drive the development of next-gen communications ASICs in a fast-paced environment.

K2 Space Seattle, WA $120k–$225k/yr Published 2 months ago

Oscilloscopes Verilog AMD JTAG Xilinx

Flexible on stack

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Senior Engineer, FPGA

Drive the development of FPGA images for pre-silicon prototyping at Ambiq, focusing on energy-efficient semiconductor solutions.

Ambiq Singapore Published 4 months ago

Xilinx Vivado MSPI Verilog USB C

Flexible on stack

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Senior Firmware Engineer, FPGA

Join CoreWeave as a Senior Firmware Engineer to design and maintain FPGA-based platform functionality for next-generation AI compute systems.

Coreweave New York, NY / Sunnyvale, CA $182k–$242k/yr Published 4 months ago

PCIe C++ Verilog C UART

Flexible on stack

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Sr. ASIC Design Engineer (Starshield)

SpaceX Hawthorne, CA $160k–$225k/yr Published 6 months ago

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

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