"chip level packaging" Jobs

276 open tech roles matching “chip level packaging”, taken straight from company career pages — not reposted from other job boards. Every listing is re-checked daily and closed roles are removed.

No "chip level packaging" jobs in Berlin right now — showing "chip level packaging" jobs in all locations.

Showing 20 of 276 results

Senior Serdes Characterization & Post-Silicon Validation Engineer

Join K2 Space as a SerDes Characterization & Post-Silicon Validation Engineer to validate high-speed interfaces in cutting-edge satellite technology.

K2 Space Seattle, WA $170k–$250k/yr Published 4 weeks ago

TX PAM4 NRZ RX Python

Flexible on stack

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Sr. ASIC Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Engineer to develop cutting-edge ASICs for space and ground infrastructures.

SpaceX Irvine, CA $165k–$265k/yr Published 2 weeks ago

Verilog ASIC Python System Verilog SoC

Flexible on stack

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Sr. ASIC Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Engineer to develop next-generation ASICs for the Starlink network.

SpaceX Redmond, WA $165k–$270k/yr Published 2 weeks ago

Verilog ASIC Python System Verilog SoC

Flexible on stack

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Director - Post-Silicon Validation (Functional)

Lead a team in post-silicon validation of cutting-edge AI chips and platforms at Graphcore's new AI Engineering Campus in Austin.

Graphcore Austin, Texas, United States Published 1 week ago

C++ FPGA ASIC Python Linux

Flexible on stack

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MTS, Agent Research

Lead research on self-improving agents to enhance engineering tasks at Etched, a frontier AI hardware startup.

Etched San Jose Published 3 weeks ago

AI/ML SFT RL

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Strategic Finance & Compute Lead

Lead the compute strategy and partnerships at Ricursive Intelligence, a frontier AI lab focused on chip design.

Ricursive Intelligence Palo Alto Published 1 week ago

compute infrastructure AI/ML chip design commercial agreements financial modeling

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FPGA/ASIC Design Engineer (Silicon Engineering) Visa

Join SpaceX as an FPGA/ASIC Design Engineer to develop cutting-edge chips for the Starlink network.

SpaceX Irvine, CA $125k–$195k/yr Published 2 weeks ago

C++ Xilinx Vivado Verilog DSP HDL simulators

Flexible on stack

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Senior Serdes Characterization & Post-Silicon Validation Engineer

Join K2 Space as a SerDes Characterization & Post-Silicon Validation Engineer to validate high-speed interfaces in cutting-edge satellite technology.

K2 Space Los Angeles, CA $170k–$250k/yr Published 4 weeks ago

TX PAM4 NRZ RX Python

Flexible on stack

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Head of Supercomputing

Lead the architecture and operational model for AI supercomputing systems at Etched, driving innovation in a fast-paced environment.

Etched San Jose Published 6 months ago

AI infrastructure custom accelerators AI/ML HPC

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Summer 2027 Silicon Engineering Internship/Co-op Visa

Join SpaceX as a silicon engineering intern to work on custom silicon and hardware for space applications.

SpaceX Flexible - Any SpaceX Site $30–$40/hr Published 2 months ago

C++ Verilog ANSYS COMSOL SPICE

Flexible on stack

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Sr. ASIC Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Palo Alto, CA $175k–$280k/yr Published 3 months ago

ASIC VMM Python UVM OVM

Flexible on stack

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Sr. ASIC Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Redmond, WA $165k–$260k/yr Published 3 months ago

ASIC VMM Python UVM OVM

Flexible on stack

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Sr. ASIC Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Irvine, CA $165k–$260k/yr Published 3 months ago

ASIC VMM Python UVM OVM

Flexible on stack

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Senior Supplier Quality Engineer - Camera

Join Skydio as a Senior Supplier Quality Engineer to ensure quality across camera supply chains for advanced drone technology.

Skydio San Mateo, California, United States $145k–$219k/yr Published 1 week ago

Mechanical Engineering Optical Engineering Quality Engineering image quality Manufacturing Engineering

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Spring 2027 Silicon Engineering Internship/Co-op Visa

Join SpaceX as a silicon engineering intern to work on cutting-edge chip design and development for space applications.

SpaceX Flexible - Any SpaceX Site $30–$40/hr Published 2 months ago

C++ Verilog ANSYS COMSOL SPICE

Flexible on stack

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Principal Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Redmond, WA $210k–$300k/yr Published 4 months ago

FPGA ASIC VMM Python UVM

Flexible on stack

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Principal Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Palo Alto, CA $210k–$310k/yr Published 4 months ago

FPGA ASIC VMM Python UVM

Flexible on stack

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Principal Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Irvine, CA $210k–$300k/yr Published 4 months ago

FPGA ASIC VMM Python UVM

Flexible on stack

Apply →

FPGA/ASIC Design Engineer (Silicon Engineering) Visa

Join SpaceX as an FPGA/ASIC Design Engineer to develop cutting-edge chips for the Starlink network.

SpaceX Redmond, WA $125k–$200k/yr Published 2 weeks ago

C++ Xilinx Vivado Verilog DSP HDL simulators

Flexible on stack

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Technical Program Manager, Hardware Systems Hybrid Visa

Own the execution of hardware systems from concept through production deployment in a fast-paced AI environment.

Anthropic San Francisco, CA | New York City, NY $365k–$435k/yr Published 2 months ago

hardware systems supply chain Firmware ODM CM

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