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SpaceX
RTL Design Engineer (Silicon Engineering) Visa
SpaceX Irvine, CA $125k–$175k/yr Published 2 months ago
APB Verilog AHB DSP Python
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SpaceX
Sr. RTL Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. RTL Design Engineer to develop cutting-edge ASICs for the Starlink network, enabling global connectivity.

SpaceX Irvine, CA $160k–$225k/yr Published 1 week ago
Verilog ASIC Python System Verilog SoC
Flexible on stack
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SpaceX
Principal DFT Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal DFT Engineer to lead the development of next-generation ASICs for the Starlink network.

SpaceX Irvine, CA $200k–$285k/yr Published 1 week ago
C++ Verilog Siemens Tessent RTL DFT
Flexible on stack
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SpaceX
Principal ASIC Design Engineer (Starshield) Visa
SpaceX Irvine, CA $200k–$285k/yr Published 1 month ago
Xilinx Vivado Verilog IES Altera Quartus II Spyglass
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SpaceX
Sr. ASIC Design Engineer (Starshield)
SpaceX Irvine, CA $160k–$225k/yr Published 1 month ago
Xilinx Vivado Verilog IES Altera Quartus II Spyglass
Apply →

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