joblaze

Direct from source · No middlemen

Uvm Jobs

32 open positions · Updated 1 month ago

Average salary (USD/year): 178.6k–291.9k/yr

32 roles Mid 11, Senior 9, Principal 6, Staff 4, Director 2 1–12 yrs experience Austin, TX +16 more Full-time newest 1 week ago

Also hiring: Python SystemVerilog ASIC OVM Perl TCL

32 Uvm roles across 10 companies, most in Other; typical advertised salary $167.5k

Who is hiring (10 companies)

SpaceX (14) Graphcore (4) K2 Space (4) Ambiq (3) ChipAgents (2)

Role types

Other (26) AI/ML (3) Design (2) Product (1)

Work arrangement: 4 hybrid · 5 on-site · 23 not stated

Advertised salaries: p25 $130.8k · median $167.5k · p75 $190k (from 20 disclosed annual salaries, USD)

Counts are open roles Joblaze currently tracks on company career pages for this exact skill/location; salaries are advertised minimums, annual, converted to USD.

Showing 12 of 32 positions

Search with filters →

Sr. ASIC Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Austin, TX Published 1 month ago

ASIC VMM Python UVM OVM

Flexible on stack

Apply →

Sr. ASIC Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Palo Alto, CA $175k–$280k/yr Published 1 month ago

ASIC VMM Python UVM OVM

Flexible on stack

Apply →

Sr. ASIC Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Redmond, WA $165k–$260k/yr Published 1 month ago

ASIC VMM Python UVM OVM

Flexible on stack

Apply →

Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop next-generation ASICs for the Starlink network.

SpaceX Irvine, CA $125k–$195k/yr Published 1 month ago

Python UVM SystemVerilog MATLAB

Flexible on stack

Apply →

Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Austin, TX Published 1 month ago

Python UVM SystemVerilog MATLAB

Flexible on stack

Apply →

Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Palo Alto, CA $135k–$210k/yr Published 1 month ago

Python UVM SystemVerilog MATLAB

Flexible on stack

Apply →

Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop cutting-edge ASICs for the Starlink network, enhancing global connectivity.

SpaceX Redmond, WA $125k–$195k/yr Published 1 month ago

Python UVM SystemVerilog MATLAB

Flexible on stack

Apply →

Research Engineer, Chip Design RL (Reinforcement Learning) Hybrid Visa

Join Anthropic as a Research Engineer to advance AI models' silicon design capabilities within a hybrid work environment.

Anthropic San Francisco, CA | New York City, NY $500k–$850k/yr Published 2 months ago

EDA RTL FPGA reinforcement learning ASIC

Flexible on stack

Apply →

Principal Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Irvine, CA $210k–$300k/yr Published 3 months ago

FPGA ASIC VMM Python UVM

Flexible on stack

Apply →

Principal Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Austin, TX Published 3 months ago

FPGA ASIC VMM Python UVM

Flexible on stack

Apply →

Principal Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Palo Alto, CA $210k–$310k/yr Published 3 months ago

FPGA ASIC VMM Python UVM

Flexible on stack

Apply →

Principal Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Redmond, WA $210k–$300k/yr Published 3 months ago

FPGA ASIC VMM Python UVM

Flexible on stack

Apply →

← Prev Page 2 of 2