Join Ambiq as a Staff Engineer, DFT, focusing on low-power DFT architecture and infrastructure for ultra-low power SoCs.
Posted by employer 3 days ago
First seen on Joblaze 2 days ago
Last verified on the company career page 11 hours ago
What you'll build
- Responsible for scan insertion, boundary scan, MBIST, ATPG
- Develop and implement low-power DFT architecture
- Generate structural test vectors
- Perform pre/post-layout scan and MBIST simulations
- Work with test engineers to bring up test vectors on silicon
Must have
- BS/MS in ECE/EE
- 8+ years of experience in DFT implementation
- Skilled in different types of DFT structures
- Experience in creating and implementing hierarchical DFT architecture
- Experience in Low-Power DFT and MBIST
- Experience in RTL
Nice to have
- Experience in scripting like Tcl
- Experience with GLS
- Strong verbal and written English communication skills
Requirements
- Experience
- 8+ years
- Education
- Master's degree
Not disclosed in this posting: compensation, work arrangement, visa sponsorship.
Joblaze summary
The Staff Engineer in DFT at Ambiq focuses on implementing low-power design for test (DFT) architectures for ultra-low power system-on-chips (SoCs), utilizing standard EDA tools for tasks like scan insertion and boundary scan. Key skills include expertise in various DFT structures, test vector generation, and collaboration with design and test engineering teams to optimize test coverage and efficiency. This role is suited for seasoned engineers with a strong background in DFT implementation and a minimum of eight years of experience. Ambiq's environment encourages innovation and collaboration, making it ideal for self-motivated problem-solvers.
Joblaze insights
Quick facts
- How much experience is required?
- At least 8 years of relevant experience for this Staff Engineer, DFT role.
- What's the tech stack?
- Joblaze extracted these technologies from the posting: DFT, EDA, MBIST, RTL, SoC, TCL.
- What seniority level is this role?
- Ambiq targets staff-level candidates for this position.
- Is this full-time or contract?
- Full-time for this Staff Engineer, DFT role at Ambiq.
From the original posting
Company Overview
Responsibilities
- Responsible for scan insertion, boundary scan, MBIST, ATPG for ultra-low power SoC based on subthreshold operation using standard EDA tools.
- Develop and implement low-power DFT architecture and infrastructure.
- Generate structural test vectors, analyse, and improve coverage, test time and test cost.
- Perform pre/post-layout scan and MBIST simulations.
- Work with designers on STA, physical, power and logical issues related to DFT.
- Work with test engineers to bring up test vectors on silicon.
Qualifications
- BS/MS in ECE/EE and at least 8 years of experience in DFT implementation.
- Skilled in different types of DFT structures, including scan (Stuck-At, At-Speed, Path-Delay), scan compression, boundary scan and MBIST.
- Experience in creating and implementing hierarchical DFT architecture in complex SoC.
- Experience in Low-Power DFT and MBIST.
- Experience in test time and test coverage analysis for scan and MBIST patterns.
- Experience in working with test engineering team to bring up production test program.
- Extensive knowledge of timing concepts and constraint development.
- Experience in developing scan ATPG and MBIST test benches and simulation in pre/post-layout environments.
- Experience in RTL is required.
- Experience in scripting like Tcl is preferred.
- Experience with GLS (gate level simulation) is preferred.
- Motivated, self-driven engineer with attention to detail.
- Strong verbal and written English communication skills.
Standard company text repeated across Ambiq's postings is omitted here.
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