Join Ambiq as a Staff Engineer - DFT to develop low-power DFT architecture for ultra-low power SoCs.
Posted by employer 7 months ago
First seen on Joblaze 1 month ago
Last verified on the company career page 1 day ago
Requirements
- Experience
- 10+ years
- Education
- Master's degree
Not disclosed in this posting: compensation, work arrangement, visa sponsorship.
Joblaze summary
In this role, the Staff Engineer for DFT at Ambiq focuses on implementing low-power design for test (DFT) strategies for ultra-low power system-on-chip (SoC) solutions. Key skills include expertise in scan insertion, boundary scan, and MBIST, along with proficiency in EDA tools and scripting languages like Tcl. This position is ideal for seasoned engineers with a strong background in DFT implementation and a collaborative mindset, as they will work closely with design and test engineering teams to enhance test coverage and efficiency. Ambiq's fast-paced environment encourages innovation and problem-solving, making it a fitting place for those eager to contribute to cutting-edge technology.
Joblaze insights
Quick facts
- How much experience is required?
- At least 10 years of relevant experience for this Staff Engineer - DFT role.
- What's the tech stack?
- Joblaze extracted these technologies from the posting: ATPG, DFT, EDA, MBIST, RTL, SoC.
- What seniority level is this role?
- Ambiq targets staff-level candidates for this position.
- Is this full-time or contract?
- Full-time for this Staff Engineer - DFT role at Ambiq.
From the original posting
Company Overview
Responsibilities
- Responsible for scan insertion, boundary scan, MBIST, ATPG for ultra-low power SoC based on subthreshold operation using standard EDA tools.
- Develop and implement low-power DFT architecture and infrastructure.
- Generate structural test vectors, analyse, and improve coverage, test time and test cost.
- Perform pre/post-layout scan and MBIST simulations.
- Work with designers on STA, physical, power and logical issues related to DFT.
- Work with test engineers to bring up test vectors on silicon.
Qualifications
- BS/MS in ECE/EE and at least 10 years of experience in DFT implementation.
- Skilled in different types of DFT structures, including scan (Stuck-At, At-Speed, Path-Delay), scan compression, boundary scan and MBIST.
- Experience in creating and implementing hierarchical DFT architecture in complex SoC.
- Experience in Low-Power DFT and MBIST.
- Experience in test time and test coverage analysis for scan and MBIST patterns.
- Experience in working with test engineering team to bring up production test program.
- Extensive knowledge of timing concepts and constraint development.
- Experience in developing scan ATPG and MBIST test benches and simulation in pre/post-layout environments.
- Experience in RTL is required.
- Experience in scripting like Tcl is preferred.
- Experience with GLS (gate level simulation) is preferred.
- Motivated, self-driven engineer with attention to detail.
- Strong verbal and written English communication skills.
Standard company text repeated across Ambiq's postings is omitted here.