Joblaze summary

In this role, the Staff Engineer for DFT at Ambiq focuses on implementing low-power design for test (DFT) strategies for ultra-low power system-on-chip (SoC) solutions. Key skills include expertise in various DFT structures, scan insertion, and boundary scan, along with a solid understanding of timing concepts and RTL. This position is ideal for seasoned engineers with over a decade of experience in DFT implementation, particularly those who thrive in fast-paced environments and enjoy tackling complex technical challenges.

Joblaze insights

Listed about a month ago — first seen on Joblaze September 3, 2026. Last confirmed on Ambiq's careers page October 27, 2026.
TCL appears in 1.5% of 273 comparable staff other roles in United States; ATPG appears in 0.4% of 273 comparable staff other roles in United States.

Quick facts

How much experience is required?: At least 10 years of relevant experience for this Senior Engineer - DFT role.
What's the tech stack?: Joblaze extracted these technologies from the posting: ATPG, DFT, EDA, MBIST, RTL, SoC.
What seniority level is this role?: Ambiq targets staff-level candidates for this position.
Is this full-time or contract?: Full-time for this Senior Engineer - DFT role at Ambiq.

From the original posting

Company Overview

Responsibilities

Responsible for scan insertion, boundary scan, MBIST, ATPG for ultra-low power SoC based on subthreshold operation using standard EDA tools.
Develop and implement low-power DFT architecture and infrastructure.
Generate structural test vectors, analyse, and improve coverage, test time and test cost.
Perform pre/post-layout scan and MBIST simulations.
Work with designers on STA, physical, power and logical issues related to DFT.
Work with test engineers to bring up test vectors on silicon.

Qualifications

BS/MS in ECE/EE and at least 10 years of experience in DFT implementation.
Skilled in different types of DFT structures, including scan (Stuck-At, At-Speed, Path-Delay), scan compression, boundary scan and MBIST.
Experience in creating and implementing hierarchical DFT architecture in complex SoC.
Experience in Low-Power DFT and MBIST.
Experience in test time and test coverage analysis for scan and MBIST patterns.
Experience in working with test engineering team to bring up production test program.
Extensive knowledge of timing concepts and constraint development.
Experience in developing scan ATPG and MBIST test benches and simulation in pre/post-layout environments.
Experience in RTL is required.
Experience in scripting like Tcl is preferred.
Experience with GLS (gate level simulation) is preferred.
Motivated, self-driven engineer with attention to detail.
Strong verbal and written English communication skills.

Standard company text repeated across Ambiq's postings is omitted here.

Senior Engineer - DFT

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