"rtl" Jobs

9 open tech roles matching “rtl”, taken straight from company career pages — not reposted from other job boards. Most in demand right now: ASIC, Python, Verilog. Every listing is re-checked daily and closed roles are removed.

Showing 9 of 9 results

Sr. RTL Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. RTL Design Engineer to develop cutting-edge ASICs for the Starlink network, enabling global connectivity.

SpaceX Palo Alto, CA $170k–$235k/yr Published 3 months ago

Verilog ASIC Python System Verilog SoC

Flexible on stack

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Principal DFT Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal DFT Engineer to develop next-generation ASICs for the Starlink network, enhancing global connectivity.

SpaceX Palo Alto, CA $220k–$355k/yr Published 3 weeks ago

C++ Verilog Siemens Tessent DFT ASIC

Flexible on stack

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ASIC/SOC DFT Engineer (Silicon Engineering) Visa

Join SpaceX as an ASIC/SOC DFT Engineer to develop cutting-edge ASICs for the Starlink network, enabling global connectivity.

SpaceX Palo Alto, CA $135k–$175k/yr Published 2 weeks ago

Verilog UPF RTL DFT ASIC

Flexible on stack

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Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Palo Alto, CA $135k–$210k/yr Published 1 month ago

Python UVM SystemVerilog MATLAB

Flexible on stack

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Sr. ASIC Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Palo Alto, CA $175k–$280k/yr Published 1 month ago

ASIC VMM Python UVM OVM

Flexible on stack

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Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. SOC/ASIC Physical Design Engineer to develop cutting-edge silicon for space and ground infrastructures.

SpaceX Palo Alto, CA $170k–$230k/yr Published 2 months ago

FinFET bash ASIC Python Perl

Flexible on stack

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Physical Design Engineer II (Silicon Engineering) Visa

SpaceX Palo Alto, CA $155k–$185k/yr Published 3 months ago

FinFET EDA Makefile ASIC Python

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Principal Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Palo Alto, CA $210k–$310k/yr Published 3 months ago

FPGA ASIC VMM Python UVM

Flexible on stack

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New Graduate Engineer, Silicon Engineering Visa

Join SpaceX as a New Graduate Engineer in Silicon Engineering, working on next-gen silicon for the Starlink program.

SpaceX Palo Alto, CA $135k–$175k/yr Published 1 week ago

ADS Verilog HFSS RTL Momentum

Flexible on stack

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