"ahb" Jobs

11 open tech roles matching “ahb”, taken straight from company career pages — not reposted from other job boards. Most in demand right now: Verilog, Python, System Verilog. Every listing is re-checked daily and closed roles are removed.

Showing 11 of 11 results

Sr. Staff Engineer - Digital Design Verification Visa

Join Ambiq as a Sr. Staff Engineer to lead digital design verification for cutting-edge low-power semiconductor solutions.

Ambiq Austin, Texas, United States Published 3 months ago

APB Verilog ARM AHB C/C++

Flexible on stack

Apply →

Sr. Staff Engineer - Digital Design Verification Visa

Join Ambiq as a Sr. Staff Engineer to lead digital design verification for cutting-edge low-power semiconductor solutions.

Ambiq Austin, Texas, United States Published 2 weeks ago

APB Verilog ARM AHB C/C++

Flexible on stack

Apply →

Sr. Staff SoC RTL Engineer

Join Ambiq as a Senior Staff SoC RTL Engineer to design and deliver ultra-low-power semiconductor solutions.

Ambiq Austin, Texas, United States Published 1 month ago

APB Verilog ARM AHB FPGA

Flexible on stack 70% coding

Apply →

Sr. Staff SoC Power & Performance Architect Visa

Join Ambiq as a Sr. Staff Power & Performance Architect to drive power and performance analysis for low-power SoCs in Austin.

Ambiq Austin, Texas, United States Published 3 weeks ago

Cadence Joules Synopsys PrimePower Python TCL Siemens PowerPro

Flexible on stack

Apply →

Sr. ASIC Design Engineer (Starshield)

SpaceX Hawthorne, CA $160k–$225k/yr Published 5 months ago

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

Apply →

Manager, ASIC Design Engineering (Starshield Silicon) Visa

SpaceX Hawthorne, CA $190k–$245k/yr Published 4 months ago

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

Apply →

Principal ASIC Design Engineer (Starshield) Visa

SpaceX Hawthorne, CA $200k–$285k/yr Published 5 months ago

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

Apply →

Sr. RTL Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. RTL Design Engineer to develop cutting-edge ASICs for the Starlink network, enabling global connectivity.

SpaceX Irvine, CA $160k–$225k/yr Published 3 months ago

Verilog ASIC Python System Verilog SoC

Flexible on stack

Apply →

Sr. RTL Design Engineer (Silicon Engineering) Visa

SpaceX Austin, TX Published 6 months ago

Verilog AHB ASIC Python System Verilog

Apply →

Sr. RTL Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. RTL Design Engineer to develop cutting-edge ASICs for the Starlink network, enabling global connectivity.

SpaceX Palo Alto, CA $170k–$235k/yr Published 3 months ago

Verilog ASIC Python System Verilog SoC

Flexible on stack

Apply →

Sr. RTL Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. RTL Design Engineer to develop cutting-edge ASICs for the Starlink network, enhancing global connectivity.

SpaceX Redmond, WA $160k–$225k/yr Published 3 months ago

Verilog ASIC Python System Verilog SoC

Flexible on stack

Apply →