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Principal Systemverilog Jobs

3 open positions · Updated 3 hours ago

Average salary: 203.3k–288.3k/yr

Showing 3 of 3 positions

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Principal ASIC Design Verification Engineer (Starshield) Visa

Python UVM SystemVerilog MATLAB

USA

$200k–$285k/yr

Published 1 month ago Apply →

Principal ASIC Design Verification Engineer (Starshield) Visa

Python UVM SystemVerilog MATLAB

Hawthorne, CA

$200k–$285k/yr

Published 1 month ago Apply →

Principal ASIC Design Verification Engineer (Starshield) Visa

Python UVM SystemVerilog MATLAB

Palo Alto, CA

$210k–$295k/yr

Published 4 weeks ago Apply →

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