Joblaze summary

The Emulation Engineer at Etched is responsible for bringing up hardware prototypes, ensuring that RTL from design teams operates effectively on the platform. Key skills include hands-on FPGA prototyping experience, proficiency in SystemVerilog and Verilog, and strong scripting abilities for automation. This role is suited for engineers with a solid background in hardware development and debugging, particularly those who thrive in collaborative environments that bridge multiple technical disciplines.

Joblaze insights

Listed about a month ago — first seen on Joblaze September 21, 2026. Last confirmed on Etched's careers page November 10, 2026.
Salary band is above the typical range for comparable tech roles (median ~$128,000).
Starts above 93% of 348 comparable mid other roles in United States that list Python we track (median $110,000 across 64 companies). See Python salary trends
Python appears in 18.1% of 3377 comparable mid other roles in United States; Synopsys appears in 0.1% of 3377 comparable mid other roles in United States.

Quick facts

Is the Emulation Engineer, Hardware Prototyping (HAPS) role remote?: No — this is an on-site role in San Jose.
What's the salary range?: Etched lists $150,000–$275,000 for this role.
Where is the role based?: Etched is hiring for this position in San Jose.
What's the tech stack?: Joblaze extracted these technologies from the posting: C, C++, FPGA, HAPs, Linux, Protium.
What seniority level is this role?: Etched targets mid-level candidates for this position.
Is this full-time or contract?: Full-time for this Emulation Engineer, Hardware Prototyping (HAPS) role at Etched.

From the original posting

What you'll do

Own HAPS bring-up. Take RTL from the design teams and get it running on the prototype — partitioning, multi-FPGA timing closure, clocking, memory mapping, and full-chip assembly.
Expand platform coverage. Stand up new subsystem configurations so more of the chip is available to software earlier. Each new partition you enable unblocks a team.
Support your users. Firmware, driver, and software engineers are your customers. You'll help them get running, triage their failures, and figure out whether the bug is theirs, the RTL's, or the platform's.
Debug hard problems. Trace issues across FPGA boundaries with waveform capture, protocol analyzers, and whatever tooling you have to build yourself.
Bring up interfaces. PCIe, Ethernet, HBM and memory models, JTAG, I2C, UART, QSPI — both the models and the physical bridges.
Build the flows. Automate builds, regressions, and image delivery so the platform scales past the number of people who understand it.
Work across the org. Design, DV, Silicon Validation, Performance, Firmware, and Software — plus direct partnership with Synopsys on tool issues and platform capability.

Representative projects

Bring up a new subsystem partition on HAPS and get firmware booting on it end to end.
Build a self-service flow that lets software users load and run their own images without prototyping support in the loop.
Instrument deep trace capture across partition boundaries and build the tooling that surfaces it usefully.
Create configurable chip-to-chip and off-chip interface models using prototyping-efficient primitives.
Close timing on a partition that doesn't want to close, and document how you did it so the next person doesn't have to rediscover it.

You may be a good fit if you have

Hands-on FPGA prototyping experience — HAPS, Protium, proFPGA, S2C, or similar — covering partitioning, synthesis, timing closure, bring-up, and debug.
Strong SystemVerilog and Verilog, with a working understanding of what synthesizes well for FPGA and what doesn't.
Solid C/C++ and Linux system development.
Scripting fluency for automation — Python, TCL, shell.
Comfort debugging failures you didn't cause, in code you didn't write, for users who need an answer today.

Strong candidates may also have

Experience with ProtoCompiler, Vivado, or Synopsys prototyping flows.
Firmware, driver, or bootloader bring-up experience on pre-silicon platforms.
Experience with emulation platforms (ZeBu, Palladium, Veloce) alongside prototyping — we run both, and the collateral is shared.
UVM verification environments, DFT, and testbench modeling.
Waveform debug tooling: Verdi, SimVision.
Cluster and job scheduling experience (SLURM), CI systems.

Benefits

Medical, dental, and vision packages with generous premium coverage
- $500 per month credit for waiving medical benefits
Daily lunch and dinner in our office
Unlimited compute budget subject to ROI justification

Compensation Range

$150,000 - $275,000

Standard company text repeated across Etched's postings is omitted here.

Emulation Engineer, Hardware Prototyping (HAPS)

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