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Systemverilog Jobs

60 open positions · Updated 1 week ago

Average salary (USD/year): 147.4k–228.5k/yr

60 roles Senior 20, Mid 16, Principal 9, Staff 9, Junior 3, Director 2, Intern 1 1–20 yrs experience Austin, TX +20 more Full-time, Internship newest 1 week ago

Also hiring: Python C++ Verilog UVM TCL VHDL

60 Systemverilog roles across 12 companies, most in Other; typical advertised salary $135k

Who is hiring (12 companies)

K2 Space (16) SpaceX (14) Graphcore (9) Neuralink (6) Ambiq (5)

Role types

Other (54) AI/ML (4) Design (2)

Work arrangement: 6 hybrid · 10 on-site · 44 not stated

Advertised salaries: p25 $125k · median $135k · p75 $170k (from 37 disclosed annual salaries, USD)

Counts are open roles Joblaze currently tracks on company career pages for this exact skill/location; salaries are advertised minimums, annual, converted to USD.

Showing 20 of 60 positions

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Director, Silicon Verification

Lead the verification strategy for Graphcore's AI accelerators, driving high-quality silicon delivery in a global team.

Graphcore Bristol, UK Published 9 months ago

C++ JavaScript LLVM Git XSLT

Flexible on stack

FPGA Engineer Visa

Join Cowboy Space Corp as an FPGA Engineer to design and implement cutting-edge optical communication systems for space applications.

Cowboy Space Corporation San Carlos, California $150k–$200k/yr Published 1 week ago

Vitis Verilog AMD Xilinx Zynq UltraScale+

FPGA Engineer Visa

Join Astranis as an FPGA Engineer to design and verify high-performance systems for advanced satellites.

Astranis San Francisco $140k–$205k/yr Published 2 years ago

RF Verilog Vivado IDE DSP DAC

Flexible on stack

Senior Firmware Engineer, FPGA

Join CoreWeave as a Senior Firmware Engineer to design and maintain FPGA-based platform functionality for next-generation AI compute systems.

Coreweave New York, NY / Sunnyvale, CA $182k–$242k/yr Published 2 months ago

PCIe C++ Verilog UART Intel/Altera

Flexible on stack

Senior FPGA Engineer

Join Northwood Space as a Senior FPGA Engineer to design and implement advanced communication systems for satellite missions.

Northwood Space Torrance, CA Published 2 weeks ago

C++ Verilog DSP Rust FPGA

Flexible on stack

New Graduate Engineer, Silicon Engineering Visa

Join SpaceX as a New Graduate Engineer in Silicon Engineering to develop next-generation silicon for the Starlink program.

SpaceX Redmond, WA $125k–$165k/yr Published 4 weeks ago

ADS Verilog DSP HFSS RTL

Flexible on stack

New Graduate Engineer, Silicon Engineering Visa

Join SpaceX as a New Graduate Engineer in Silicon Engineering to develop next-generation silicon for the Starlink program.

SpaceX Irvine, CA $125k–$160k/yr Published 4 weeks ago

ADS Verilog HFSS RTL Momentum

Flexible on stack

New Graduate Engineer, Silicon Engineering Visa

Join SpaceX as a New Graduate Engineer in Silicon Engineering, working on next-gen silicon for the Starlink program.

SpaceX Palo Alto, CA $135k–$175k/yr Published 4 weeks ago

ADS Verilog HFSS RTL Momentum

Flexible on stack

ASIC/SOC DFT Engineer (Silicon Engineering) Visa

Join SpaceX as an ASIC/SOC DFT Engineer to develop cutting-edge ASICs for the Starlink network, enabling global connectivity.

SpaceX Palo Alto, CA $135k–$175k/yr Published 1 month ago

Verilog UPF RTL DFT ASIC

Flexible on stack

ASIC/SOC DFT Engineer (Silicon Engineering) Visa

Join SpaceX as an ASIC/SOC DFT Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Austin, TX Published 1 month ago

Verilog RTL DFT bash ASIC

Flexible on stack

FPGA Engineer Hybrid Visa

Join Northwood Space as an FPGA Engineer to design and develop advanced communication systems for satellite missions.

Northwood Space Torrance, CA $100k–$160k/yr Published 1 month ago

C++ Verilog DSP FPGA SoCs Rust

Flexible on stack

Principal DFT Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal DFT Engineer to lead the development of next-generation ASICs for the Starlink network.

SpaceX Irvine, CA $210k–$340k/yr Published 1 month ago

C++ Verilog Siemens Tessent DFT ASIC

Flexible on stack

Principal DFT Engineer (Silicon Engineering) Visa

Lead the implementation and optimization of DFT architectures for next-generation ASICs at SpaceX.

SpaceX Austin, TX Published 1 month ago

C++ Verilog Siemens Tessent UPF DFT

Flexible on stack

Principal DFT Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal DFT Engineer to develop next-generation ASICs for the Starlink network, enhancing global connectivity.

SpaceX Palo Alto, CA $220k–$355k/yr Published 1 month ago

C++ Verilog Siemens Tessent DFT ASIC

Flexible on stack

Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop cutting-edge ASICs for the Starlink network, enhancing global connectivity.

SpaceX Redmond, WA $125k–$195k/yr Published 1 month ago

Python UVM SystemVerilog MATLAB

Flexible on stack

Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Austin, TX Published 1 month ago

Python UVM SystemVerilog MATLAB

Flexible on stack

Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Palo Alto, CA $135k–$210k/yr Published 1 month ago

Python UVM SystemVerilog MATLAB

Flexible on stack

Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop next-generation ASICs for the Starlink network.

SpaceX Irvine, CA $125k–$195k/yr Published 1 month ago

Python UVM SystemVerilog MATLAB

Flexible on stack

FPGA/ASIC Design Engineer (Silicon Engineering) Visa

Join SpaceX as an FPGA/ASIC Design Engineer to develop cutting-edge chips for the Starlink network, enhancing global connectivity.

SpaceX Redmond, WA $125k–$175k/yr Published 3 months ago

C++ Xilinx Vivado Verilog DSP HDL simulators

Flexible on stack

RTL Design Engineer (Silicon Engineering) Visa

SpaceX Irvine, CA $125k–$175k/yr Published 5 months ago

APB Verilog AHB DSP Python

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