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UVM Jobs in United States

31 open positions · Updated 2 months ago

Average salary (USD/year): 173.9k–273.1k/yr

31 roles Mid 12, Senior 10, Intern 4, Staff 3, Principal 2 1–12 yrs experience Austin +13 more Full-time, Internship newest 1 day ago

Also hiring: SystemVerilog Python TCL Perl Verilog FPGA

31 UVM roles across 8 companies, most in Other; 6% fully remote; typical advertised salary $165k

Who is hiring (8 companies)

SpaceX (10) Etched (6) Astranis (5) K2 Space (4) Ambiq (3)

Role types

Other (27) AI/ML (2) Design (2)

Work arrangement: 2 fully remote · 3 hybrid · 7 on-site · 19 not stated

Advertised salaries: p25 $131k · median $165k · p75 $175k (from 17 disclosed annual salaries, USD)

Counts are open roles Joblaze currently tracks on company career pages for this exact skill/location; salaries are advertised minimums, annual, converted to USD.

Showing 11 of 31 positions

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FPGA Engineer Visa

Join Astranis as an FPGA Engineer to design and verify high-performance systems for advanced satellites.

Astranis San Francisco $140k–$205k/yr Published 2 years ago

RF Verilog Vivado IDE DSP DAC

Flexible on stack

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AMS Verification Engineer (RFIC Engineering) Visa

Join SpaceX as an AMS Verification Engineer to develop cutting-edge RFICs for the Starlink network.

SpaceX Redmond, WA $125k–$200k/yr Published 2 months ago

AMS Verilog-A RFIC Python UVM

Flexible on stack

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AMS Verification Engineer (RFIC Engineering) Visa

Join SpaceX as an AMS Verification Engineer to develop cutting-edge RFICs for the Starlink network.

SpaceX Irvine, CA $125k–$160k/yr Published 2 months ago

AMS Verilog-A RFIC Python UVM

Flexible on stack

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Sr. ASIC Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Austin, TX Published 4 months ago

ASIC VMM Python UVM OVM

Flexible on stack

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Sr. ASIC Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Palo Alto, CA $175k–$280k/yr Published 4 months ago

ASIC VMM Python UVM OVM

Flexible on stack

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Sr. ASIC Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Irvine, CA $165k–$260k/yr Published 4 months ago

ASIC VMM Python UVM OVM

Flexible on stack

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Sr. ASIC Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Redmond, WA $165k–$260k/yr Published 4 months ago

ASIC VMM Python UVM OVM

Flexible on stack

Apply →

Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Austin, TX Published 4 months ago

Python UVM SystemVerilog MATLAB

Flexible on stack

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Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop cutting-edge ASICs for the Starlink network, enhancing global connectivity.

SpaceX Redmond, WA $125k–$195k/yr Published 4 months ago

Python UVM SystemVerilog MATLAB

Flexible on stack

Apply →

Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Palo Alto, CA $135k–$210k/yr Published 4 months ago

Python UVM SystemVerilog MATLAB

Flexible on stack

Apply →

Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop next-generation ASICs for the Starlink network.

SpaceX Irvine, CA $125k–$195k/yr Published 4 months ago

Python UVM SystemVerilog MATLAB

Flexible on stack

Apply →

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