"testbenches" Jobs

26 open tech roles matching “testbenches”, taken straight from company career pages — not reposted from other job boards. Most in demand right now: UVM, SystemVerilog, Python. Every listing is re-checked daily and closed roles are removed.

Showing 20 of 26 results

Design Verification Engineer - Internal IP Hybrid

Join Etched as a Design Verification Engineer to ensure high-performance custom IPs for cutting-edge AI hardware.

Etched Austin Published 5 months ago

Python UVM Perl TCL SystemVerilog

Flexible on stack

Apply →

Design Verification Engineer - Internal IP

Join Etched as a Design Verification Engineer to ensure high-performance custom IPs for cutting-edge AI hardware.

Etched San Jose Published 1 year ago

Python UVM Perl TCL SystemVerilog

Flexible on stack

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Emulation Engineer, Hardware Prototyping (HAPS)

Join Etched as an Emulation Engineer to own HAPS bring-up and support firmware and software engineers in a cutting-edge AI hardware startup.

Etched San Jose $150k–$275k/yr Published 4 months ago

C++ Protium Verilog SimVision palladium

Flexible on stack

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Design Verification Engineer - SoC Hybrid

Join Etched as a Design Verification Engineer to ensure high-performance custom IPs for cutting-edge AI hardware.

Etched Austin Published 5 months ago

Python SystemVerilog

Flexible on stack

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Design Verification Engineer - SoC

Join Etched as a Design Verification Engineer to ensure high-performance custom IPs for cutting-edge AI hardware.

Etched San Jose Published 1 year ago

Python SystemVerilog

Flexible on stack

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Sr. Staff Engineer - Digital Design Verification Visa

Join Ambiq as a Sr. Staff Engineer to lead digital design verification for cutting-edge low-power semiconductor solutions.

Ambiq Austin, Texas, United States Published 1 month ago

APB Verilog ARM AHB C/C++

Flexible on stack

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Sr. Staff Engineer - Digital Design Verification Visa

Join Ambiq as a Sr. Staff Engineer to lead digital design verification for cutting-edge low-power semiconductor solutions.

Ambiq Austin, Texas, United States Published 4 months ago

APB Verilog ARM AHB C/C++

Flexible on stack

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Design Verification Engineer - Interface IP Hybrid

Join Etched as a Design Verification Engineer to tackle complex verification challenges in a fast-paced startup environment.

Etched Austin Published 5 months ago

PCIe ARC ARM UVM SystemVerilog

Flexible on stack

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Design Verification Engineer - Interface IP

Join Etched as a Design Verification Engineer to tackle complex verification challenges in a fast-paced startup environment.

Etched San Jose Published 1 year ago

PCIe ARC ARM UVM SystemVerilog

Flexible on stack

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Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop next-generation ASICs for the Starlink network.

SpaceX Irvine, CA $125k–$195k/yr Published 2 months ago

Python UVM SystemVerilog MATLAB

Flexible on stack

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Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Austin, TX Published 2 months ago

Python UVM SystemVerilog MATLAB

Flexible on stack

Apply →

Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Palo Alto, CA $135k–$210k/yr Published 2 months ago

Python UVM SystemVerilog MATLAB

Flexible on stack

Apply →

Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop cutting-edge ASICs for the Starlink network, enhancing global connectivity.

SpaceX Redmond, WA $125k–$195k/yr Published 2 months ago

Python UVM SystemVerilog MATLAB

Flexible on stack

Apply →

AMS Verification Engineer (RFIC Engineering) Visa

Join SpaceX as an AMS Verification Engineer to develop cutting-edge RFICs for the Starlink network.

SpaceX Redmond, WA $125k–$200k/yr Published 1 month ago

AMS Verilog-A RFIC Python UVM

Flexible on stack

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AMS Verification Engineer (RFIC Engineering) Visa

Join SpaceX as an AMS Verification Engineer to develop cutting-edge RFICs for the Starlink network.

SpaceX Irvine, CA $125k–$160k/yr Published 1 month ago

AMS Verilog-A RFIC Python UVM

Flexible on stack

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Senior ASIC Design Verification Engineer

Join K2 Space as a Senior ASIC Design Verification Engineer to shape first-generation silicon in a fast-paced, high-growth environment.

K2 Space United States - Remote $170k–$250k/yr Published 3 months ago

Python UVM Perl TCL SystemVerilog

Flexible on stack

Apply →

Applied AI Engineer, Silicon Engineering

Join Etched as an Applied AI Engineer to enhance chip development using AI agents in a hands-on, onsite role.

Etched San Jose Published 3 months ago

C++ Ray Slurm EDA RTL

Flexible on stack

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Senior ASIC Design Verification Engineer

Join K2 Space as a Senior ASIC Design Verification Engineer to shape first-generation silicon in a fast-paced, high-growth environment.

K2 Space Seattle, WA $170k–$250k/yr Published 3 months ago

Python UVM Perl TCL SystemVerilog

Flexible on stack

Apply →

Principal ASIC Design Verification Engineer

Join K2 Space as a Principal ASIC Design Verification Engineer to shape first-generation silicon in a high-growth environment.

K2 Space United States - Remote $190k–$285k/yr Published 3 months ago

C++ Python UVM Perl TCL

Flexible on stack

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Principal ASIC Design Verification Engineer

Join K2 Space as a Principal ASIC Design Verification Engineer to shape first-generation silicon in a fast-paced, high-growth environment.

K2 Space Seattle, WA $190k–$285k/yr Published 3 months ago

C++ Python UVM Perl TCL

Flexible on stack

Apply →