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TCL Jobs
64 open positions · Updated 1 month ago
64 TCL roles across 10 companies, most in Other; typical advertised salary $160k
Who is hiring (10 companies)
Role types
Work arrangement: 2 hybrid · 18 on-site · 44 not stated
Advertised salaries: p25 $135k · median $160k · p75 $180k (from 25 disclosed annual salaries, USD)
Counts are open roles Joblaze currently tracks on company career pages for this exact skill/location; salaries are advertised minimums, annual, converted to USD.
Showing 20 of 64 positions
Search with filters →Join Graphcore as a Staff Silicon Logical Design Engineer to deliver high-quality microarchitecture and RTL for AI computing systems.
Join Graphcore as a Silicon Physical Design Engineer to work on cutting-edge AI superchips in a collaborative environment.
Join Graphcore as a Senior Physical Design Engineer in Bengaluru, contributing to the development of next-gen AI superchips.
Join Graphcore as a Senior Silicon Logical Design Engineer to contribute to high-quality microarchitecture and RTL for AI computing systems.
Lead and scale the Logical Design group at Graphcore, ensuring high-quality RTL and microarchitecture for advanced chip designs.
Join Graphcore as a DFT Engineer to work on next-generation AI designs for data centers, contributing to the future of AI compute.
Join Astranis as an FPGA Engineer to design and verify high-performance systems for advanced satellites.
Join SpaceX as a Principal DFT Engineer to develop next-generation ASICs for the Starlink network, enhancing global connectivity.
Lead the implementation and optimization of DFT architectures for next-generation ASICs at SpaceX.
Join SpaceX as a Principal DFT Engineer to lead the development of next-generation ASICs for the Starlink network.
Join SpaceX as an EDA Engineer to support and improve IC design environments for cutting-edge satellite technology.
Join SpaceX as an EDA Engineer to enhance IC design environments for cutting-edge satellite technology.
Join SpaceX as a Sr. ASIC DFT Engineer to develop next-generation ASICs for the Starlink network, enhancing global connectivity.
Join SpaceX as a Sr. Full Chip Physical Verification Engineer to develop cutting-edge silicon for the Starlink network.
Join SpaceX as a Sr. ASIC DFT Engineer to develop next-generation ASICs for the Starlink network, enabling global connectivity.
Join SpaceX as a Sr. ASIC DFT Engineer to develop next-generation ASICs for the Starlink network, enhancing global connectivity.
Join SpaceX as a Sr. SOC/ASIC Physical Design Engineer to develop cutting-edge silicon for space and ground infrastructures.
Join SpaceX as a Sr. SOC/ASIC Physical Design Engineer to develop cutting-edge silicon for space and ground infrastructures.