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TCL Jobs
63 open positions · Updated 1 month ago
63 TCL roles across 9 companies, most in Other; typical advertised salary $160k
Who is hiring (9 companies)
Role types
Work arrangement: 2 hybrid · 18 on-site · 43 not stated
Advertised salaries: p25 $134k · median $160k · p75 $178.8k (from 24 disclosed annual salaries, USD)
Counts are open roles Joblaze currently tracks on company career pages for this exact skill/location; salaries are advertised minimums, annual, converted to USD.
Showing 20 of 63 positions
Search with filters →Join Graphcore as a Staff Silicon Physical Design Engineer in Bengaluru, contributing to the development of next-gen AI superchips.
Join Ricursive Intelligence as a Chip Design Engineer to architect AI-driven physical design flows for advanced chip development.
Lead verification of FPGA designs for safety-critical applications in portable nuclear microreactors at a pioneering startup.
Join Neuralink as an Analog IC Layout Engineer to innovate in chip design for brain-computer interfaces.
Join K2 Space as a Senior ASIC Design Verification Engineer to shape first-generation silicon in a fast-paced, high-growth environment.
Join K2 Space as a Senior ASIC Design Verification Engineer to shape first-generation silicon in a fast-paced, high-growth environment.
Join Ambiq as a Sr. Staff Power & Performance Architect to drive power and performance analysis for low-power SoCs in Austin.
Join Ambiq as a Staff Power Validation Engineer to lead power validation strategies for ultra-low-power SoCs in a collaborative environment.
Join Ambiq as a Senior Analog Validation Engineer to validate and characterize analog subsystems in ultra-low-power SoCs.
Join Ambiq as a Memory Design Engineer to innovate ultra-low power memory solutions for advanced SoC products.
Lead the silicon validation organization at Ambiq, driving post-silicon validation strategy for SoCs and edge AI products.
Join Graphcore as a Silicon Physical Design Engineer to work on cutting-edge AI superchips in a collaborative environment.
Join Graphcore as a Staff Silicon Logical Design Engineer to deliver high-quality microarchitecture and RTL for AI computing systems.