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Tcl Jobs
55 open positions · Updated 1 week ago
55 Tcl roles across 9 companies, most in Other; typical advertised salary $160k
Who is hiring (9 companies)
Role types
Work arrangement: 1 hybrid · 13 on-site · 41 not stated
Advertised salaries: p25 $133k · median $160k · p75 $170k (from 27 disclosed annual salaries, USD)
Counts are open roles Joblaze currently tracks on company career pages for this exact skill/location; salaries are advertised minimums, annual, converted to USD.
Showing 20 of 55 positions
Search with filters →Join Ambiq as a Sr. Staff Power & Performance Architect to drive power and performance analysis for low-power SoCs in Austin.
Join Ambiq as a Senior Analog Validation Engineer to validate and characterize analog subsystems in ultra-low-power SoCs.
Lead the silicon validation organization at Ambiq, driving post-silicon validation strategy for SoCs and edge AI products.
Join Ambiq as a Memory Design Engineer to innovate ultra-low power memory solutions for advanced SoC products.
Join Graphcore as a Silicon Physical Design Engineer to work on cutting-edge AI superchips in a collaborative environment.
Join Graphcore as a Staff/Principal Logical Design Engineer to contribute to innovative AI compute technologies.
Join Graphcore as a Staff Silicon Logical Design Engineer to deliver high-quality microarchitecture and RTL for AI computing systems.
Join Graphcore as a Senior Physical Design Engineer in Bengaluru, contributing to the development of next-gen AI superchips.
Join Graphcore as a Senior Silicon Logical Design Engineer to contribute to high-quality microarchitecture and RTL for AI computing systems.
Lead and scale the Logical Design group at Graphcore, ensuring high-quality RTL and microarchitecture for advanced chip designs.
Join Graphcore as a DFT Engineer to work on next-generation AI designs for data centers, contributing to the future of AI compute.
Join Astranis as an FPGA Engineer to design and verify high-performance systems for advanced satellites.
Join SpaceX as a Principal DFT Engineer to lead the development of next-generation ASICs for the Starlink network.
Join SpaceX as a Principal DFT Engineer to develop next-generation ASICs for the Starlink network, enhancing global connectivity.
Lead the implementation and optimization of DFT architectures for next-generation ASICs at SpaceX.
Join SpaceX as an EDA Engineer to support and improve IC design environments for cutting-edge satellite technology.