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Senior Systemverilog Jobs

4 open positions · Updated 1 month ago

Average salary: 162.5k–227.5k/yr

Showing 4 of 4 positions

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Sr. ASIC Design Verification Engineer (Starshield) Visa

SpaceX Irvine, CA $160k–$225k/yr Published 2 months ago

Python UVM SystemVerilog MATLAB

Sr. ASIC Design Verification Engineer (Starshield) Visa

SpaceX Hawthorne, CA $160k–$225k/yr Published 2 months ago

Python UVM SystemVerilog MATLAB

Sr. ASIC Design Verification Engineer (Starshield) Visa

SpaceX Palo Alto, CA $170k–$235k/yr Published 2 months ago

Python UVM SystemVerilog MATLAB

Sr. FPGA Engineer (Starshield) Visa

SpaceX Hawthorne, CA $160k–$225k/yr Published 4 months ago

C++ Verilog DSP FPGA SystemVerilog

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