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Senior Systemverilog Jobs

17 open positions · Updated 3 weeks ago

Average salary: 141.9k–211.9k/yr
17 roles Mid 9, Junior 3, Principal 3, Intern 1, Senior 1 1–10 yrs experience Austin, TX +5 more Full-time, Internship newest 1 week ago
Also hiring: Python Verilog ASIC C++ VHDL DFT

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Northwood Space
Senior FPGA Engineer Visa

Join Northwood as a Senior FPGA Engineer to design and implement cutting-edge space communication systems.

Northwood Space Torrance, CA $160k–$275k/yr Published 1 month ago
C++ Verilog DSP Rust FPGA
Flexible on stack
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