24 TCL roles across 8 companies, most in Other; typical advertised salary $165k
Who is hiring (8 companies)
Role types
Work arrangement: 1 hybrid · 7 on-site · 16 not stated
Advertised salaries: p25 $160k · median $165k · p75 $170k (from 10 disclosed annual salaries, USD)
Counts are open roles Joblaze currently tracks on company career pages for this exact skill/location; salaries are advertised minimums, annual, converted to USD.
Showing 20 of 24 positions
Search with filters →Join Ricursive Intelligence as a DFT Engineer to shape the future of chip design with AI-driven methodologies.
Lead silicon validation and test program development for large-format AI accelerator chips at a cutting-edge startup.
Own block-level implementation from synthesis through GDSII sign-off as a Physical Design Engineer at a cutting-edge AI hardware startup.
Join Etched as a DFT Engineer to enhance testability and product quality in cutting-edge integrated circuits.
Join Ricursive Intelligence as a Chip Design Engineer to architect AI-driven physical design flows for advanced chip development.
Lead verification of FPGA designs for safety-critical applications in portable nuclear microreactors at a pioneering startup.
Join K2 Space as a Senior ASIC Design Verification Engineer to shape first-generation silicon in a fast-paced, high-growth environment.
Join K2 Space as a Senior ASIC Design Verification Engineer to shape first-generation silicon in a fast-paced, high-growth environment.
Join Ambiq as a Senior Analog Validation Engineer to validate and characterize analog subsystems in ultra-low-power SoCs.
Join Graphcore as a Senior Physical Design Engineer in Bengaluru, contributing to the development of next-gen AI superchips.
Join Graphcore as a Senior Silicon Logical Design Engineer to contribute to high-quality microarchitecture and RTL for AI computing systems.
Join SpaceX as a Sr. ASIC DFT Engineer to develop next-generation ASICs for the Starlink network, enabling global connectivity.
Join SpaceX as a Sr. Full Chip Physical Verification Engineer to develop cutting-edge silicon for the Starlink network.
Join SpaceX as a Sr. ASIC DFT Engineer to develop next-generation ASICs for the Starlink network, enhancing global connectivity.
Join SpaceX as a Sr. ASIC DFT Engineer to develop next-generation ASICs for the Starlink network, enhancing global connectivity.
Join SpaceX as a Sr. SOC/ASIC Physical Design Engineer to develop cutting-edge silicon for space and ground infrastructures.