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Verilog Jobs

51 open positions · Updated 1 month ago

Average salary (USD/year): 153.2k–238.4k/yr

51 roles Mid 15, Senior 13, Intern 10, Principal 6, Staff 4, Lead 2, Director 1 0–20 yrs experience Austin, TX +21 more Full-time, Internship newest 3 days ago

Also hiring: Python SystemVerilog C++ TCL FPGA C

51 Verilog roles across 15 companies, most in Other; 2% fully remote; typical advertised salary $150k

Who is hiring (15 companies)

SpaceX (18) Ambiq (8) Astranis (6) Etched (4) Graphcore (2)

Role types

Other (44) AI/ML (4) Design (2) Management (1)

Work arrangement: 1 fully remote · 1 hybrid · 11 on-site · 38 not stated

Advertised salaries: p25 $125k · median $150k · p75 $177.5k (from 23 disclosed annual salaries, USD)

Counts are open roles Joblaze currently tracks on company career pages for this exact skill/location; salaries are advertised minimums, annual, converted to USD.

Showing 20 of 51 positions

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Silicon Validation Engineer, Software

Join Etched as a Silicon Validation Engineer to develop firmware for AI/ML accelerator ASICs in a hands-on, onsite role.

Etched San Jose Published 2 months ago

C++ Verilog C CI/CD JTAG

Flexible on stack

Emulation Engineer, Hardware Prototyping (HAPS)

Join Etched as an Emulation Engineer to own HAPS bring-up and support firmware and software engineers in a cutting-edge AI hardware startup.

Etched San Jose $150k–$275k/yr Published 5 months ago

C++ Protium Verilog SimVision palladium

Flexible on stack

DFT Intern

Join Etched as a DFT Intern to refine DFT flow automation and contribute to chip-level regression in a fast-paced environment.

Etched San Jose Published 6 months ago

Verilog Python TCL SystemVerilog

Flexible on stack

ASIC Architect

Join Etched as an ASIC Architect to design next-generation AI accelerators with a focus on performance and efficiency.

Etched San Jose Published 1 year ago

C++ Verilog C gem5 AI/ML

Flexible on stack Heavy meetings

FPGA Manager

Lead and grow the FPGA team responsible for developing complex electronic hardware for air-to-air radar systems.

Reliable Robotics Corporation Seattle, WA Published 1 week ago

Verilog radar algorithms Radar signal processing DO-254 VHDL

Senior FPGA Engineer Visa

Join Astranis as a Senior FPGA Engineer to design and verify RTL for advanced satellite systems.

Astranis San Francisco $175k–$240k/yr Published 2 years ago

C++ Verilog C DSP Vivado

Flexible on stack

Electrical Engineer, Compute Architecture

Join Neuralink as an Electrical Engineer to design and oversee custom electronics systems for innovative healthcare solutions.

Neuralink Austin, Texas, United States; South San Francisco, California, United States $105k–$175.5k/yr Published 5 months ago

PCIe MIPI Verilog LVDS SLVS-EC

Flexible on stack

Signal Processing Engineer

Join Neuralink as a Signal Processing Engineer to develop advanced DSP algorithms for brain-computer interface devices.

Neuralink Austin, Texas, United States; South San Francisco, California, United States $121k–$230.5k/yr Published 6 months ago

Verilog C Signal Processing Python VHDL

Flexible on stack

Senior FPGA Prototyping Engineer

Join K2 Space as a Senior FPGA Prototyping Engineer to drive the development of next-gen communications ASICs in a fast-paced environment.

K2 Space Seattle, WA $120k–$225k/yr Published 2 months ago

Oscilloscopes Verilog AMD JTAG Xilinx

Flexible on stack

Senior FPGA Prototyping Engineer

Join K2 Space as a Senior FPGA Prototyping Engineer to drive the development of next-gen communications ASICs in a fast-paced environment.

K2 Space United States - Remote $120k–$225k/yr Published 2 months ago

Verilog AMD UART JTAG Xilinx

Flexible on stack

Sr. Staff Engineer - Digital Design Verification Visa

Join Ambiq as a Sr. Staff Engineer to lead digital design verification for cutting-edge low-power semiconductor solutions.

Ambiq Austin, Texas, United States Published 2 months ago

APB Verilog ARM AHB C/C++

Flexible on stack

Sr. Staff SoC RTL Engineer

Join Ambiq as a Senior Staff SoC RTL Engineer to design and deliver ultra-low-power semiconductor solutions.

Ambiq Austin, Texas, United States Published 3 months ago

APB Verilog ARM AHB FPGA

Flexible on stack 70% coding

Staff Engineer - Design Verification

Join Ambiq as a Staff Engineer to verify digital and mixed-signal designs for low-power semiconductor solutions.

Ambiq Singapore Published 4 months ago

C++ Verilog ARM C Makefile

Flexible on stack

Senior Engineer, FPGA

Drive the development of FPGA images for pre-silicon prototyping at Ambiq, focusing on energy-efficient semiconductor solutions.

Ambiq Singapore Published 4 months ago

Xilinx Vivado MSPI Verilog USB C

Flexible on stack

Sr. Staff Engineer - Digital Design Verification Visa

Join Ambiq as a Sr. Staff Engineer to lead digital design verification for cutting-edge low-power semiconductor solutions.

Ambiq Austin, Texas, United States Published 4 months ago

APB Verilog ARM AHB C/C++

Flexible on stack

Principal SoC RTL Engineer

Join Ambiq as a Principal RTL Engineer to drive architecture and RTL development for next-generation silicon in a dynamic team.

Ambiq Austin, Texas, United States Published 7 months ago

IP Verilog MCU SystemVerilog SoC

Silicon DFT Engineer — Multiple Levels

Join Graphcore as a DFT Engineer to work on next-generation AI designs for data centers, contributing to the future of AI compute.

Graphcore Bristol, UK; Cambridge, UK Published 9 months ago

IJTAG Core Test Test Compression Verilog Shell

FPGA Engineer Visa

Join Astranis as an FPGA Engineer to design and verify high-performance systems for advanced satellites.

Astranis San Francisco $140k–$205k/yr Published 2 years ago

RF Verilog Vivado IDE DSP DAC

Flexible on stack

Senior Firmware Engineer, FPGA

Join CoreWeave as a Senior Firmware Engineer to design and maintain FPGA-based platform functionality for next-generation AI compute systems.

Coreweave New York, NY / Sunnyvale, CA $182k–$242k/yr Published 4 months ago

PCIe C++ Verilog C UART

Flexible on stack

ASIC/SOC DFT Engineer (Silicon Engineering) Visa

Join SpaceX as an ASIC/SOC DFT Engineer to develop cutting-edge ASICs for the Starlink network, enabling global connectivity.

SpaceX Palo Alto, CA $135k–$175k/yr Published 2 months ago

Verilog UPF RTL DFT ASIC

Flexible on stack

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