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Verilog Jobs

40 open positions · Updated 4 weeks ago

Average salary (USD/year): 148.2k–224.9k/yr

40 roles Senior 13, Mid 11, Principal 5, Staff 5, Junior 3, Intern 2, Lead 1 0–20 yrs experience Austin, TX +20 more Full-time, Internship newest 1 week ago

Also hiring: Python SystemVerilog FPGA C++ ASIC VHDL

40 Verilog roles across 12 companies, most in Other; typical advertised salary $135k

Who is hiring (12 companies)

SpaceX (19) Ambiq (6) Graphcore (2) K2 Space (2) Neuralink (2)

Role types

Other (35) AI/ML (2) Design (2) Management (1)

Work arrangement: 3 hybrid · 9 on-site · 28 not stated

Advertised salaries: p25 $125k · median $135k · p75 $165k (from 23 disclosed annual salaries, USD)

Counts are open roles Joblaze currently tracks on company career pages for this exact skill/location; salaries are advertised minimums, annual, converted to USD.

Showing 20 of 40 positions

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New Graduate Engineer, Silicon Engineering Visa

Join SpaceX as a New Graduate Engineer in Silicon Engineering, working on next-gen silicon for the Starlink program.

SpaceX Palo Alto, CA $135k–$175k/yr Published 4 weeks ago

ADS Verilog HFSS RTL Momentum

Flexible on stack

New Graduate Engineer, Silicon Engineering Visa

Join SpaceX as a New Graduate Engineer in Silicon Engineering to develop next-generation silicon for the Starlink program.

SpaceX Redmond, WA $125k–$165k/yr Published 4 weeks ago

ADS Verilog DSP HFSS RTL

Flexible on stack

New Graduate Engineer, Silicon Engineering Visa

Join SpaceX as a New Graduate Engineer in Silicon Engineering to develop next-generation silicon for the Starlink program.

SpaceX Irvine, CA $125k–$160k/yr Published 4 weeks ago

ADS Verilog HFSS RTL Momentum

Flexible on stack

ASIC/SOC DFT Engineer (Silicon Engineering) Visa

Join SpaceX as an ASIC/SOC DFT Engineer to develop cutting-edge ASICs for the Starlink network, enabling global connectivity.

SpaceX Palo Alto, CA $135k–$175k/yr Published 1 month ago

Verilog UPF RTL DFT ASIC

Flexible on stack

ASIC/SOC DFT Engineer (Silicon Engineering) Visa

Join SpaceX as an ASIC/SOC DFT Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Austin, TX Published 1 month ago

Verilog RTL DFT bash ASIC

Flexible on stack

FPGA Engineer Hybrid Visa

Join Northwood Space as an FPGA Engineer to design and develop advanced communication systems for satellite missions.

Northwood Space Torrance, CA $100k–$160k/yr Published 1 month ago

C++ Verilog DSP FPGA SoCs Rust

Flexible on stack

Summer 2027 Silicon Engineering Internship/Co-op Visa

Join SpaceX as a silicon engineering intern to work on custom silicon and hardware for space applications.

SpaceX Flexible - Any SpaceX Site $30–$40/hr Published 1 month ago

C++ Verilog ANSYS COMSOL SPICE

Flexible on stack

Spring 2027 Silicon Engineering Internship/Co-op Visa

Join SpaceX as a silicon engineering intern to work on cutting-edge chip design and development for space applications.

SpaceX Flexible - Any SpaceX Site $30–$40/hr Published 1 month ago

C++ Verilog ANSYS COMSOL SPICE

Flexible on stack

Principal DFT Engineer (Silicon Engineering) Visa

Lead the implementation and optimization of DFT architectures for next-generation ASICs at SpaceX.

SpaceX Austin, TX Published 1 month ago

C++ Verilog Siemens Tessent UPF DFT

Flexible on stack

Principal DFT Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal DFT Engineer to develop next-generation ASICs for the Starlink network, enhancing global connectivity.

SpaceX Palo Alto, CA $220k–$355k/yr Published 1 month ago

C++ Verilog Siemens Tessent DFT ASIC

Flexible on stack

Principal DFT Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal DFT Engineer to lead the development of next-generation ASICs for the Starlink network.

SpaceX Irvine, CA $210k–$340k/yr Published 1 month ago

C++ Verilog Siemens Tessent DFT ASIC

Flexible on stack

Sr. RTL Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. RTL Design Engineer to develop cutting-edge ASICs for the Starlink network, enabling global connectivity.

SpaceX Irvine, CA $160k–$225k/yr Published 3 months ago

Verilog ASIC Python System Verilog SoC

Flexible on stack

Sr. RTL Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. RTL Design Engineer to develop cutting-edge ASICs for the Starlink network, enhancing global connectivity.

SpaceX Redmond, WA $160k–$225k/yr Published 3 months ago

Verilog ASIC Python System Verilog SoC

Flexible on stack

Sr. RTL Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. RTL Design Engineer to develop cutting-edge ASICs for the Starlink network, enabling global connectivity.

SpaceX Palo Alto, CA $170k–$235k/yr Published 3 months ago

Verilog ASIC Python System Verilog SoC

Flexible on stack

FPGA/ASIC Design Engineer (Silicon Engineering) Visa

Join SpaceX as an FPGA/ASIC Design Engineer to develop cutting-edge chips for the Starlink network, enhancing global connectivity.

SpaceX Redmond, WA $125k–$175k/yr Published 3 months ago

C++ Xilinx Vivado Verilog DSP HDL simulators

Flexible on stack

Manager, ASIC Design Engineering (Starshield Silicon) Visa

SpaceX Hawthorne, CA $190k–$245k/yr Published 4 months ago

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

Sr. RTL Design Engineer (Silicon Engineering) Visa

SpaceX Austin, TX Published 6 months ago

Verilog AHB ASIC Python System Verilog

Sr. ASIC Design Engineer (Starshield)

SpaceX Hawthorne, CA $160k–$225k/yr Published 5 months ago

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

RTL Design Engineer (Silicon Engineering) Visa

SpaceX Irvine, CA $125k–$175k/yr Published 5 months ago

APB Verilog AHB DSP Python

Principal ASIC Design Engineer (Starshield) Visa

SpaceX Hawthorne, CA $200k–$285k/yr Published 5 months ago

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

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